Samsung Electronics Co., Ltd.

Do Soo Jeong

Kyu Jin Lee

Hyeon J Jeong

Min Cheol An

Hai Jeong Sohn

Dong Ho Lee

Young Jae Song

Tae Je Cho

Seung H Ahn

Ki Won Choi

Tae Gyeong Chung

Jae June Kim

Kwan Jai Lee

Wan Gyan Choi

Chang Cheol Lee

Kyung Seob Kim

Jong Hee Choi

Suk Hong Chang

Beung Seuck Song

A method for manufacturing a chip scale package comprises preparing a tape wiring board that includes a polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the tape, a window formed in the tape to enable the Cu traces to be connected to a semiconductor chip attached below the board, multiple connection holes formed in the tape to expose portions of the Cu traces therethrough and define solder ball mounting pads, and an elastomer chip carrier attached to the bottom surface of the tape. The method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads. The pre-flux and the cover sheet each prevents the solder ball mounting pads being plated with gold. This, in turn, prevents the formation of intermetallic compounds in the solder balls so that the bond strength between the solder balls and a pad to which they attach is improved.

Method for manufacturing a chip scale package having copper traces selectively plated with gold

A semiconductor device package includes a die pad to which a semiconductor chip is vertically attached, having a smaller horizontal size than a horizontal size of the semiconductor chip. The package includes a plurality of inner leads which are electrically connected to the semiconductor chip, a plurality of outer leads each of which is integral with a respective one of the plurality of inner leads, a tie bar, and a package body for encapsulating the semiconductor chip, the die pad, and the plurality of inner leads. The tie bar for supporting the die pad has a downward bend effecting a downward vertical displacement from the die pad, and has a laterally spaced apart upward bend effecting an upward vertical displacement from the die pad. This package prevents imperfect encapsulation and resulting problems such as cracking of the package, and reduces damage to the die pad, such as warping of the die pad.

Semiconductor device package having twice-bent tie bar and small die pad

A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips. The auxiliary leads can also be positioned to prevent undesirable spreading of an adhesive when an upper chip is attached to a lower chip.

Multi-chip package

A package for a semiconductor chip including a plurality of input/output pads includes an insulating layer and a plurality of conductive traces. The insulating layer has a first surface for bonding with the surface of the semiconductor chip so that the input/output pads are exposed adjacent the insulating layer. The conductive traces are provided on a second surface of the insulating layer opposite the first surface wherein each of the conductive traces corresponds to a respective one of the input/output pads. In particular, the conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads. Accordingly, each of the bonding wires can be bonded at a first end to the respective input/output pad and at a second end to the respective conductive trace. Furthermore, the input/output pads can be on an interior portion of the surface of the semiconductor chip, and the insulating layer can have an opening therein for exposing the input/output pads. Accordingly, a dam on the second surface of the insulating layer can be provided around the opening wherein each of the conductive traces extends from adjacent the opening under the dam to a portion of the insulating layer outside the dam. Related methods and assemblies are also discussed.

Wire bond packages for semiconductor chips and related methods and

A method for manufacturing a chip-size package and the chip-size package produced by the method uses first and second lead frames which are prepared by a stamping process. The first lead frame has leads with receiving parts, and the leads are integrally formed with lengthwise side rails of the lead frame. The second lead frame has external connections which align with the receiving parts of the leads when the second lead frame is positioned on top of the first lead frame and attached thereto. Guide holes located on the crosswise side rails of both lead frames can be used to easily align the two lead frames. A semiconductor chip is then adhered to the underside of the first lead frame, and the bonding pads of the semiconductor chip are electrically connected to the leads of the first lead frame. Then the two lead frames and the chip are encapsulated, with only the external connections of the second lead frame remaining exposed to the outside. Solder balls are then attached to the external connections for mounting onto a substrate. This chip-size package is inexpensive to produce, because the first and second lead frames can be produced by a stamping process, which is less complex and cheaper than the conventional half-etching process.

Chip-size package (CSP) using a multi-layer laminated lead frame

Lead frames for semiconductor chips include spaced apart tie-bars which extend to contact and support the semiconductor chip. Adhesive is used between the tie-bars and the chip to adhesively couple the tie-bars to the chip. The lead frame leads therefore need not be used to adhesively couple the chip to the lead frame, thereby reducing or eliminating the need for equal spacing and close coupling of the leads, and reducing or preventing problems caused by deterioration of adhesive on the leads. The tie-bars may include polyimide tape or liquid adhesive held in cups. During fabrication, a semiconductor chip is mounted on the adhesive material, such that the tie-bars mechanically support the semiconductor chip and the lead ends extend adjacent the semiconductor chip. The lead ends are then electrically connected to the semiconductor chip and the package is encapsulated.

Lead frames including extended tie-bars, and semiconductor chip packages

A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device. The leads of the upper lead frame are formed to directly contact top surfaces of the inner leads of the lower lead frame, so that the upper and the lower parts can be electrically interconnected. An insulating adhesive film is interposed between the upper semiconductor chip and the inner leads of the lower lead frame.

Stacked chip package device employing a plurality of lead on chip type

A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, each individual semiconductor device including (1) a semiconductor chip, (2) a protective body for encapsulating the semiconductor chip, (3) a lead frame comprising inner lead portions electrically interconnected to the semiconductor chip and included within the protective body, outer lead portions formed as a single body with the inner lead portions, and coupling lead portions located between the inner and outer lead portions and having a top surface exposed upward from the protective body, and (4) a plurality of vertical interconnection elements attached to a back surface of the coupling lead portions and exposed from the protective body in a direction opposing the exposed top surface of the coupling lead portions, whereby, an electrical interconnection of the plurality of individual semiconductor devices is accomplished by the coupling lead portions and the vertical interconnection elements, and electrical interconnection of the three dimensional stack package device to an external circuit device is accomplished by the outer lead portions of a lowermost semiconductor device.

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Kyungki-do, South Korea

Do Soo Jeong