Globalfoundries Inc.

Advanced Micro Devices Corporation

Globlfoundries, Inc.

Dmytro Chumakov

Petra Hetzer

Peter Baars

Matthias Schaller

Wolfgang Buchholtz

Tino Hertzsch

Michael Grillberger

Katrin Reiche

Ehrenfried Zschech

Volker Grimm

Heike Berthold

Holm Geisler

Dirk Utess

In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

Shrinkage of critical dimensions in a semiconductor device by selective growth of a mask material

A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.

DRAM cell based on conductive nanochannel plate

In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes.

Semiconductor device comprising a buried capacitor formed in the contact level

During the fabrication of microstructure devices, such as integrated circuits, particles may be analyzed by displacing or removing the particles from the device surface and subsequently performing an analysis process. Consequently, a well-defined measurement environment may be established after removal of the particles, which may be accomplished on the basis of nanoprobes and the like. Hence, even critical surface areas may be monitored with respect to contamination and the like on the basis of well-established analysis techniques.

Method and system for particles analysis in microstructure devices by isolating particles

Methods and systems are provided for fabricating a semiconductor device. An exemplary method involves forming a feature of a semiconductor device in a first region of a layer of material on a semiconductor substrate and forming a test structure in a second region of the layer of material. The test structure is formed concurrently to forming the feature, and a dimension of the feature is determined using the test structure.

In-situ measurement of feature dimensions

In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.

Test structure for ILD void testing and contact resistance measurement in a semiconductor device

A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer.

Mask-based silicidation for FEOL defectivity reduction and yield boost

Vertical contact structures, such as contact elements connected to semiconductor-based contact regions in device areas comprising densely-spaced gate electrode structures, are formed for given lithography and patterning capabilities by incorporating at least one additional dielectric layer of superior tapering behavior into the dielectric material system.

Shrinkage of contact elements and vias in a semiconductor device by incorporating additional tapering material

An integrated circuit having a place-efficient capacitor includes a lower capacitor electrode having a surface area comprised of an inner surface area of a partial opening and a via opening formed in a patterned dielectric layer on a semiconductor substrate, a capacitor insulating layer overlying the lower capacitor electrode, and an upper capacitor electrode including a metal fill material filling the partial opening and the via opening and having a surface area that includes the inner surface area of the partial opening and via opening.

Integrated circuits having place-efficient capacitors and methods for fabricating the same

Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein.

Integrated circuit fabrication methods utilizing embedded hardmask layers for high resolution patterning

A method is provided including depositing a layer of material on a substrate, during deposition of the material, at a predetermined depth, laterally implanting a first dopant and a second dopant in the material, the second dopant being different from the first dopant, etching the material, during etching, detecting the positions and intensities of the first and second dopants, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants.

Dopant marker for precise recess control

Thermally induced stress in a semiconductor die, i.e., in a complex metallization system thereof, may be reduced by 'dividing' a package substrate into two or more substrate sections, which may have formed therebetween an appropriate stress buffer region, for instance a region of superior resiliency. In this case, the total deformation of the package substrate may be reduced, thereby also reducing the thermally induced stress forces in the complex metallization system of the semiconductor die. Hence, for a given size and complexity of a metallization system, an increased production yield and superior reliability may be achieved.

Chip package including multiple sections for reducing chip package interaction

A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.

Stress reduction in chip packaging by a stress compensation region formed around the chip

Analysis of chemical and physical characteristics of polymer species and etch residues caused in critical plasma-assisted etch processes for patterning material layers in semiconductor devices may be accomplished by removing at least a portion of these species on the basis of a probing material layer, which may be lifted-off from the patterned surface. The probing material layer may substantially suppress a chemical modification of the species of interest and may thus allow the examination of the initial status of these species.

Growing community of inventors

Dresden, Germany

Dmytro Chumakov