Advanced Micro Devices Corporation

Globalfoundries U.S. Inc.

Dirk Wollstein

Jan Raebiger

Richard P Good

Markus Nopper

Gerd Marxsen

Matthias Ruhm

Susanne Wehner

Thomas Ortleb

Roberto Schiwon

Stefan Lingel

Sylvia Boehlmann

Jan Räbiger

Andr&eacute; Holfeld

The present disclosure generally relates to a system and a method for detecting a defect in a specimen. More particularly, the present disclosure relates to a lithography exposure system and a method for detecting a dispensing error in a wafer The present disclosure provides a system for detecting a defect in a specimen having a lithography exposure tool including a measurement unit and a stage, the measurement unit is configured to obtain topography data of the specimen placed on the stage by illumination of a surface of the specimen with an optical signal, and a processor configured to generate a statistical data from the topography data and produce a defect notification if the statistical data is outside of a control limit.

System and method for detecting a defect in a specimen

A method of automatic deposition profile targeting for electrochemically depositing copper with a position-dependent controllable plating tool including the steps of depositing copper on a patterned product wafer, measuring an actual thickness profile of the deposited copper and generating respective measurement data, feeding the measurement data to an advanced process control (APC) model and calculating individual corrections for plating parameters in the position-dependent controllable plating tool.

Automatic deposition profile targeting

The present disclosure generally addresses the problem of controlling a plating profile in multi-step recipes and addresses, in particular, the problem of compensating for variations of the plating tool state to stabilize the plating results. The compensation is done by adjustments of corrections factors for currents of a plating tool in a multi-anode configuration. The described method enables control of recipes with different current ratios in each recipe step and models different deposition sensitivities in each recipe step. Generally, the method of the present disclosure requires a measurement step, where the tool state is determined, and a data processing step, where the correction factors are set based on models describing the plating process and the tool state.

Profile control on ring anode plating chambers for multi-step recipes

A method and a controller for the chemical mechanical polishing (CMP) of substrates and, in particular, for the chemical mechanical polishing of metallization layers is disclosed. In a linear model of the CMP process, the erosion of the metallization layer to be treated is determined by the overpolish time and possibly by an extra polish time on a separate polishing platen for polishing the dielectric layer, wherein the CMP inherent characteristics are represented by sensitivity parameters derived empirically. Moreover, the control operation is designed so that even with a certain inaccuracy of the sensitivity parameters due to subtle process variations, a reasonable controller response is obtained.

Method and system for controlling the chemical mechanical polishing of substrates by calculating an overpolishing time and/or a polishing time of a final polishing step

An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer contained in the layer stack is employed. Moreover, a topography factor characterizing the surface structure of the layer stack and a selectivity characterizing the ratio of removal rates between adjacent material layers are used. Furthermore, a state variable of the controller represented by the removal rate of one of the layers may periodically be updated on the basis of the previously calculated polish time and a measurement value of the finally obtained layer thickness. The improved controller is particularly advantageous in the CMP process for STI isolation structures, in which the final thickness of a CMP stop layer, having a significantly reduced removal rate compared to the overlying dielectric layer, has to be precisely controlled.

Method of controlling the chemical mechanical polishing of stacked layers having a surface topology

Methods and systems are disclosed that allow an adjustment of an electrical property of a field effect transistor during the fabrication of the device. A manufacturing process downstream of the gate electrode formation step is controlled in response to the measured gate length such that a deviation of the measured gate length is, at least partially, compensated by a subsequent process step in order to maintain the electrical property of the completed field effect transistor within specified tolerances. In one illustrative embodiment, the effective gate length that is defined as the lateral distance of lightly doped regions is controlled so as to substantially maintain it. Moreover, a controller is disclosed that allows the manufacturing of a field effect transistor on a run-to-run basis by which variations of the gate length are at least partially compensated.

Growing community of inventors

Dresden, Germany

Dirk Wollstein