Qimonda Ag

Micron Technology Incorporated

Infineon Technologies Ag

Other

Siemens Aktiengesellschaft

Lantiq Deutschland Gmbh

Qimonda

Dirk Scheideler

Peter Gregorius

Hermann Ruckerbauer

Johannes Stecker

Christoph Bilger

Maurizio Skerlj

Michael Bruennert

Roland Barth

Wolfgang Walthes

Anthony Sanders

Edoardo Prete

Georg Braun

Richard Johannes Luyken

Steve Wood

Hans-Peter Trost

Philipp Börker

Maksim Kuzmenka

Kai Schiller

Karthik S Gopalakrishnan

Otto Schumacher

Thomas Eichler

Heinz Werker

Dirk Friebe

Bruno Celli-Urbani

David Müller

Volkmar Rebmann

Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.

Wiring configuration of a bus system and power wires in a memory chip

A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Memory system with extended memory density capability

The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Method and apparatus for determining a skew

The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Multi-die memory, apparatus and multi-die memory stack

The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Memory circuit

An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Apparatus and method for providing a signal for transmission via a signal line

An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Integrated circuit with wireless connection

Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

Method and apparatus for storage device with a logic unit and method for manufacturing same

In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data, data), at least one clock signal input (Clock), at least one control signal input (Cnt_del, Cnt_del) and a data signal output (Data_out). According to the invention, the integrated circuit is configured to provide a digital data signal having a variable symbol duration at its output (Data_out), the symbol duration being controllable by means of the control signal (Cnt_del, Cnt_del). A further embodiment of the invention relates to a method for generating a digital data signal having a variable symbol duration in which an output signal is generated by at least one first data signal, at least one first clock signal and at least one control signal. For this purpose, at least one second clock signal is generated from the first clock signal, the second clock signal having a variable delay and the delay being set depending on the value of the at least one control signal. The output signal is formed from the at least one first data signal, whereby the outputting is carried out edge-synchronously to the first and the second clock signal.

Method and device for generating a digital data signal and use thereof

An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillator

An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Apparatus and method for switching an apparatus to a power saving mode

An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage

A device and method is described for the frequency division of an input clock signal, in which from the input clock signal at least two output clock signals are generated, with an output pulse frequency equal to an input pulse frequency divided by a given factor, whereby with a phase detector a phase difference is measured between the at least two output signals and each of the at least two output clock signals is either inverted or not inverted, as a function of the phase difference determined. A method of this type is particularly suitable for the demultiplexing of an input data signal, and can also be designed to be multi-step.

Method and device for frequency division and demultiplexing

A method and an apparatus for scanning a data signal are provided whereby a plurality of scanning signals (P, P, P, P) delayed successively by a respective phase difference are generated, for example, by a quadrature oscillator (). A first data signal (D) is scanned with these scanning signals (P&#x2013;P) in order to generate a plurality of second data signals (D&#x2013;D). Because the direction of rotation of the quadrature oscillator () can vary, depending on random starting conditions, the direction of rotation is determined by means of phase detectors (). These phase detectors () are preferably connected to the outputs of the clock dividers (). Depending on the direction of rotation determined, the second data signals (D&#x2013;D) are allocated to output channels (A&#x2013;A) by a change-over unit ().

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Munich, Germany

Dirk Scheideler