Infineon Technologies Ag

Nan Ya Technology Corporation

Dirk Efferenn

Hans-Peter Moll

Andreas Wich-Glasen

Jens Bachmann

Uwe Kahler

Chung-Hsin Lin

Wen-Bin Lin

Jörg Radecker

Jens Hahn

Grit Bonsdorf

Ulrike Grüning Von Schwerin

Ronald Gottzein

Lee Donohue

The invention is concerned with a process for removing residue comprising a polymeric resist and metal oxide from a metal structure on a semiconductor substrate, the process comprising the steps of: (a) heating up the substrate with the metal structure in the presence of molecular nitrogen gas (N); (b) a stabilization step in the presence of pure molecular nitrogen gas (N); (c) a passivation step employing a plasma containing at least one of the group of water, nitrogen and oxygen; and (d) a stripping step containing oxygen to remove the residue, comprising resist.

Process for removing a residue from a metal structure on a semiconductor substrate

A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.

Method for masking a recess in a structure having a high aspect ratio

A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.

Method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits

A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.

Method for fabricating a self-aligning mask

A method for fabricating a semiconductor structure includes providing a semiconductor substrate, providing a plurality of trenches in the semiconductor substrate using a first hard mask, and causing the hard mask to recede by a predetermined distance with respect to the trench wall at the top side of the semiconductor substrate for forming a first hard mask that has been caused to recede. An isolation trench structure is provided in the semiconductor substrate using a second hard mask, the isolation trench structure subdividing the first first hard mask that has been caused to recede along rows into strip sections and the strip sections of adjacent rows being arranged offset with respect to one another. The receding process results in a reduction of an overlap region between two strip sections of adjacent rows in comparison with an overlap region which would be present without the receding process. The second hard mask is removed and the isolation trench structure is filled and planarized with a filling material using the first hard mask subdivided into the strip sections.

Method for fabricating a semiconductor structure

The method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module provides the following steps. A thermal oxide layer is applied in isolation trenches. A nitride liner is subsequently applied. In a further step, a mask is applied in the region in which n-channel field-effect transistors are intended to be produced. The nitride liner is removed around the mask. Finally, the mask is also removed. As a result, the properties of the n-channel field-effect transistors are improved, without impairing the properties of the p-channel field-effect transistors.

Method for producing a shallow trench isolation for n- and p-channel field-effect transistors in a semiconductor module

A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.

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Dresden, Germany

Dirk Efferenn