Intel Corporation

Other

Dingying David Xu

Mohit Mamodia

Rahul N Manepalli

Hongxia Feng

Nachiket R Raravikar

Leonel R Arana

Meizi Jiao

Matthew L Tingey

Sheng C Li

Edward Rudolph Prack

Amram Eitan

Jung Kyu Han

Chung Kwang Christopher Tan

Kristof Darmawikarta

Saikumar Jayaraman

Brandon C Marin

Rajasekaran Swaminathan

Jeremy D Ecton

Gang Duan

Tarek A Ibrahim

Xavier Francois Brun

Nisha Ananthakrishnan

Todd P Albertson

Xiaoying Guo

Bai Nie

Mihir A Oka

Haobo Chen

David M Craig

Gregory S Constable

Hong Dong

Bohan Shan

Joseph D Stanford

Srinivas V Pietambaram

Omkar G Karhade

Zhiguo Qian

Chuan Hu

James Chris Matayabas, Jr

Yonggang Li

Yoshihiro Tomita

Digvijay Ashokkumar Raorane

Mitul Bharat Modi

Edvin Cetegen

Pramod Malatkar

Suddhasattwa Nad

Chong Zhang

Jorge A Sanchez

Sri Chaitra Jyotsna Chavali

Nicholas S Haehn

Paul J Diglio

Steve S Cho

Yiqun Bai

Kuang C Liu

Anna M Prakash

Changhua Liu

Kyle Jordan Arrington

Kyle Yazzie

Yosuke Kanaoka

Arjun Krishnan

Vijay Wakharkar

Marcel Arlan Wall

Sameer Paital

Nirupama Chakrapani

Srinivas Venkata Ramanuja Pietambaram

Jesse Jones

Shankar Ganapathysubramanian

Karumbu Meyyappan

Ziyin Lin

Jieying Kong

Wen Yin

Dale A Hackitt

Kabirkumar Mirpuri

Sarah Blythe

Akshay Mathkar

Kyle Mcelhinny

Valery Ouvarov-Bancalero

Yue Deng

Joseph Van Nausdle

Wei Wei

Santosh Tripathi

Vaibhav Agrawal

Yiyang Zhou

Javier S Gonzalez

Jason Steill

Teag R Haughan

Joaquin Aguilar-Santillan

Wen Feng

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Omni directional interconnect with magnetic fillers in mold matrix

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

Method to enable 30 microns pitch EMIB or below

A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

Package substrate z-disaggregation with liquid metal interconnects

Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

Dummy die structures of a packaged integrated circuit device

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

Selectively roughened copper architectures for low insertion loss conductive features

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Patternable die attach materials and processes for patterning

A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

Probe pins with etched tips for electrical die test

A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

Thermal head with a thermal barrier for integrated circuit die processing

Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.

Coated probe tips for plunger pins of an integrated circuit package test system

Space transformer including a substrate and a perforated plate disposed on the substrate. The substrate includes conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as an interface between an E-testing apparatus and a DUT. The perforated plate may be affixed to a surface of the substrate and includes an array of perforations through which the conductive pins may pass. The perforated plate may provide one or more of lateral pin support and protection to the underlying substrate and/or traces. The perforated plate may include a metal sheet. A polymeric material may be disposed on at least a sidewall of the perforations to electrically isolate the metal sheet from the conductive probe pins.

Space transformer with perforated metallic plate for electrical die test

Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

Stiffener tape for electronic assembly

Growing community of inventors

Chandler, AZ, United States of America

Dingying David Xu