Industrial Technology Research Institute

Tsinghua University

Ding-Ming Kwai

Yung-Fa Chou

Chang-Tzu Lin

Ting-Sheng Chen

Cheng-Wen Wu

Chih-Yen Lo

Jin-Fu Li

I-Hsuan Lee

Yun-Chao Yu

Jui-Hung Chien

Chiao-Ling Lung

Tsu-Wei Tseng

Pei-Wen Luo

Che-Wei Chou

Po-Yuan Chen

Hsiu-Chuan Shih

Kuan-Te Wu

Tzu-Min Lin

Chi-Han Lee

Chi-Kang Chen

Chi-Chun Yang

A power source analysis method includes receiving a target number, performing voltage drop analysis on a plurality of power sources in a power delivery network (PDN) to determine respective supply currents of the power sources, sorting the supply currents of the power sources, and selecting a plurality of target power sources from the power sources according to a sorted result. The total number of the selected target power sources equals the target number.

Power source tolerance analysis method and system

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

Method of yield prejudgment and bump re-assignment and computer readable storage medium

A method for generating a power distribution network (PDN) is provided. A heterogeneous circuit data is input. A plurality of horizontal power lines and a plurality of vertical power lines are determined according to the heterogeneous circuit data. A PDN model of the heterogeneous circuit is determined according to the horizontal power lines and the vertical power lines. Power consumption value is assigned to a plurality of internal nodes of the PDN model of the heterogeneous circuit. The PDN model of the heterogeneous circuit is adjusted to meet a target voltage drop limitation of the heterogeneous circuit data.

Method for generating power distribution network (PDN) model, and power distribution network analysis method and device

A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.

Memory controlling method and memory system

A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, &#x3bc; data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0&#x3c;&#x3bc;&#x3c;M.

Fault-tolerance through silicon via interface and controlling method thereof

A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.

3-D memory and built-in self-test circuit thereof

A test method for an interposer is provided. The interposer includes a plurality of conductive lines therein and a plurality of connecting contacts thereon, wherein the connecting contacts are electrically connected to the conductive lines. The test method for an interposer provides a passive transponder device. The passive transponder device includes a first circuit including an open/short test circuit and at least a pair of connecting contacts. The test method for an interposer includes contacting the connecting contacts of the first circuit in the passive transponder device with the selected contacts on the interposer to form a checking area and conducting an open-circuit or short-circuit test for the interposer through the checking area.

Test method for interposer

An apparatus and method for generating a power delivery network (PDN) of a circuit system is provided. The apparatus performs a power diagnostics on the PDN of a circuit system. According to result of the power diagnostics, a number of areas are generated and divided into at least three subsets. At least one area is selected from each of the at least three subsets, and one node is selected from each of the selected areas, and the nodes are connected sequentially to form an interconnection with at least three nodes in the PDN.

Apparatus and method for generating a power delivery network

A memory device including at least one bit-line decoding circuit, at least one word-line decoding circuit, a plurality of memory blocks, and a plurality of switches is provided. The sizes of the plurality of memory blocks include at least one first size and a second size, and the first size is greater than the second size. The plurality of memory blocks with the first size are grouped as at least one first group, and the plurality of memory blocks with the second size are grouped as at least one second group. Compared to the first group, the second group is closer to the bit-line decoding circuit and/or the word-line decoding circuit. The switches are controlled by at least one control signal, so as to enable or disable the first group and/or the second group.

Memory device

A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.

Semiconductor device stacked structure

A method for testing a TSV comprises charging a through-silicon-via under test to a first predetermined voltage level charging a capacitance device to a second predetermined voltage level; performing charge-sharing between the through-silicon-via and the capacitance device; and determining that the through-silicon-via under test is not faulty if the voltage level of the through-silicon-via after the charge-sharing step is within a predetermined range.

Method for testing through-silicon-via

An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die.

Operating method of hardwired switch

A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked.

Technology of memory repair after stacking of three-dimensional integrated circuit

A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip.

Stacked structure and stacked method for three-dimensional chip

A method for repairing an integrated circuit comprises: fabricating a first circuit, the first circuit including a plurality of regular units and a plurality of redundant units, each of the regular units being identified by an address; performing a first test on the first circuit to determine if a defective regular unit is present; activating, if the defective regular unit is present, at least a first redundant unit to replace the defective regular unit, the first redundant unit being identified by an address of the defective regular unit; performing, if the at least first redundant unit is present, a second test on the first circuit to determine if the first redundant unit is defective; and activating at least a second redundant unit to replace the defective first redundant unit, the second redundant unit being identified by the address of the defective regular unit.

Growing community of inventors

Hsinchu County, Taiwan

Ding-Ming Kwai