Taiwan Semiconductor Manufacturing Comp. Ltd.

Ding-Kang Shih

Sung-Li Wang

Clement Hsingjen Wann

Pang-Yen Tsai

Sey-Ping Sun

Chih-Hsin Ko

Hau-Yu Lin

Chin-Hsiang Lin

Neng-Kuo Chen

Gin-Chen Huang

Yi-An Lin

Chen-Feng Hsu

Meng-Chun Chang

Chia-Hung Chu

Tsungyu Hung

Keng-Chu Lin

Cheng-Hsien Wu

Yasutoshi Okuno

Shuen-Shin Liang

Hsu-Kai Chang

Peng-Wei Chu

Teng-Chun Tsai

Zhi-Chang Lin

Chun-Hsiung Lin

Chen-Han Wang

Akira Mineji

Yao-Sheng Huang

Chung-Liang Cheng

Cheng-Long Chen

Sung-li Wang

Low-resistance contacts improve performance of integrated circuit devices that feature epitaxial source/drain regions. The low resistance contacts can be used with transistors of various types, including planar field effect transistors (FETs), FinFETs, and gate-all-around (GAA) FETs. Low-resistance junctions are formed by removing an upper portion of the source/drain region and replacing it with an epitaxially-grown boron-doped silicon germanium (SiGe) material. Material resistivity can be tuned by varying the temperature during the epitaxy process. Electrical contact is then made at the low-resistance junctions.

Epitaxial structure for source/drain contact for semiconductor structure having fin structure

A strain-relaxed silicon/silicon germanium (Si/SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.

Strained nanosheets on silicon-on-insulator substrate

The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

Field effect transistors with dual silicide contact structures

The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

Channel structures for semiconductor devices

A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

Epitaxial layers in source/drain contacts and methods of forming the same

The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

Spacer structure for semiconductor device

The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.

Backside contact structures with stacked metal silicide layers for source/drain region of fin field transistors

A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

Epitaxial backside contact

Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

Source/drain feature to contact interfaces

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Wrap-around contact on FinFET

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Taipei, Taiwan

Ding-Kang Shih