Taiwan Semiconductor Manufacturing Comp. Ltd.

Ding-I Liu

Po-Hsiung Leu

Kai-Shiung Hsu

Jyh-Nan Lin

Si-Wen Liao

Wen-Long Lee

Yuh-Ta Fan

Chun-Sheng Wu

Chun-Li Lin

Lan-Hai Wang

Yong-Hung Yang

Yi-Fang Li

Wei-Ching Wu

Cheng-Tsung Wu

Chun-Jen Chen

Chia-Yu Wu

Geng-Shuoh Chang

Chih-Wei Chiang

Mao-Cheng Lin

Yen-Chan Lo

Yi-Fang Lai

Jen-Chi Chang

Jui-Fu Hsu

Chin-Feng Sun

Po-Chang Chen

Hsiang-Sheng Kung

Chih-Chiang Chiu

Hsiao-Min Chen

Kuang-Cheng Wu

Yu-Ying Lu

Jheng-Uei Hsieh

Hui-An Han

Shian-Huei Lin

Kuo-Shu Tseng

Keith Kuang-Kuo Koai

Chien-Cheng Wu

Ming-Shiou Kuo

Li Shu Chen

Fu-Shun Lo

Huan-Chieh Chen

Sung-Po Yang

Chi-Ching Lo

Jia-Wei Xu

Chia-Ming Tai

Mu-Min Hung

Chin-Feng Lin

Jing-Yang Li

Chun-Cha Kuo

Tzu-Chien Cheng

Tzu-Chun Lin

Ho-Ta Chuang

Yl-Fang Li

Jia-Wei Hsu

Lan Hai Wang

Chung-Wen Chang

A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

Electron migration control in interconnect structures

A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

Amorphous layers for reducing copper diffusion and method forming same

In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.

Method of manufacturing semiconductor device and semiconductor devices

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.

Method of manufacturing semiconductor devices and semiconductor devices

A method of making a semiconductor device includes comparing a thickness profile of a surface of a wafer with a reference value using a control unit. The method further includes transmitting a control signal to an adjustable nozzle based on the comparison of the thickness profile and the reference value. The method further includes rotating the adjustable nozzle about a longitudinal axis of the adjustable nozzle in response to the control signal.

Method of using high density plasma chemical vapor deposition chamber

A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

Semiconductor device having a multi-layer diffusion barrier and method of making the same

A high density plasma chemical vapor deposition (HDP CVD) chamber includes a nozzle including a base having a hollow center portion for conducting gas; a tip coupled to the base and having an opening formed therein for conducting gas from the base to the exterior of the nozzle. The HDP CVD chamber further includes a baffle positioned in a top portion of the HDP CVD chamber, wherein the baffle is equipped with an adjustable baffle nozzle.

High density plasma chemical vapor deposition chamber and method of using

Method of manufacturing semiconductor devices including formation of adhesion enhancement layer

Semiconductor device having multi-layer diffusion barrier and method of making the same

An Equipment Front End Module (EFEM) having a Front Opening Unified Pod (FOUP) dock and a tool access port, includes a robotic wafer handling system configured to transfer silicon wafers between a FOUP coupled to the FOUP dock and a process tool positioned for access via the tool access port. An air curtain system inside the EFEM is positioned to produce an air curtain across the tool access port while the port is open, acting to isolate the interior of the EFEM from the tool environment, and prevent passage of airborne contaminants into the EFEM via the access port.

Equipment module with enhanced protection from airborne contaminants, and method of operation

Growing community of inventors

Hsinchu, Taiwan

Ding-I Liu