Globalfoundries Inc.

Globalfoundaries Inc.

Dina Triyoso

Elke Erben

Robert Binder

Patrick Polakowski

Johannes Mueller

Hao Zhang

Sanford Chu

Klaus Hempel

Sven Schmidbauer

Konrad Seidel

Joachim Metzger

Fabian Koehler

Itasham Hussain

Gabriela Dilliway

Sergej Mutas

Rimoon Agaiby

Mark Gerard Nolan

Wenke Weinreich

One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400&#xb0; C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ALD process

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof

The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Complex circuit element and capacitor utilizing CMOS compatible antiferroelectric high-k materials

The present disclosure provides a semiconductor device comprising a substrate, an undoped HfOlayer formed over the substrate and a TiN layer formed on the HfOlayer. Herein, the undoped HfOlayer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfOlayer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfOlayer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfOlayer.

Semiconductor device with ferroelectric hafnium oxide and method for forming semiconductor device

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.

Methods for fabricating integrated circuits with fluorine passivation

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.

Methods for fabricating integrated circuits having improved spacers

Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Methods for fabricating integrated circuits with narrow, metal filled openings

Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

Methods for fabricating integrated circuits with controlled P-channel threshold voltage

Disclosed herein are various methods of forming replacement gate structures for semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity for a replacement gate structure, forming a gate insulation layer in the gate cavity and forming a layer of metal above the gate insulation layer. In this example, the method also includes forming a patterned etch mask layer above the metal layer that exposes substantially vertically oriented portions of the metal layer within the cavity and covers a substantially horizontally oriented portion of the metal layer within the cavity, performing an etching process through the patterned etch mask layer to reduce a thickness of the exposed substantially vertically oriented portions of the metal layer and removing the patterned etch mask layer.

Growing community of inventors

Dresden, Germany

Dina Triyoso