Micron Technology Incorporated

Dimitrios Pavlopoulos

Kunal Shrotri

Anish A Khandekar

Chris M Carlson

Chandra V Mouli

Haitao Liu

Guangyu Huang

Sergei V Koveshnikov

John David Hopkins

Justin B Dorhout

Jie Li

Hung-Wei Liu

Kunal R Parekh

David A Daycock

Yushi Hu

Christopher J Larsen

Ryan L Meyer

Zhiqiang Xie

Greg Light

Lifang Xu

Paolo Tessariol

Indra V Chary

Nancy M Lomeli

Erik R Byers

Damir Fazil

Merri Lyn Carlson

Joel D Peterson

Eldon Nelson

A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon

Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

Methods of forming NAND memory arrays

A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material. Elevationally-extending strings of memory cells are formed in the stack. Structure independent of method is disclosed.

Memory arrays and methods used in forming a memory array

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Integrated structures containing vertically-stacked memory cells

NAND memory arrays, devices comprising semiconductor channel material and nitrogen, and methods of forming NAND memory arrays

An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

Elevationally-extending string of memory cells individually comprising a programmable charge storage transistor and method of forming an elevationally-extending string of memory cells individually comprising a programmable charge storage transistor

An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

Arrays of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stacks

NAND memory arrays, and devices comprising semiconductor channel material and nitrogen

Methods of forming an array of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stack

A method of forming poly silicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first poly silicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Growing community of inventors

Boise, ID, United States of America

Dimitrios Pavlopoulos