Applied Materials, Inc.

Dimitri R Kioussis

Mikhail Korolik

Saravjeet Singh

Kenneth David Schatz

Alan Tso

Marlin Wijekoon

Nitin K Ingle

Karthik Janakiraman

Kwangduk Douglas Lee

Sarah Michelle Bobek

Krishna Nittala

Ratsamee Limdulpaiboon

Abhishek Dube

Benjamin Colombeau

Suketu Arun Parikh

Naomi Yoshida

Patricia M Liu

Sanjay S Natarajan

Shiyu Sun

Lin Dong

Matthias Bauer

Tushar Mandrekar

Nam Sung Kim

Myungsun Kim

Vanessa Pena

Gaetano Santoro

The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

Multi-zone gas distribution systems and methods

Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.

Methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Integrated CMOS source drain formation with advanced control

Exemplary methods for etching a germanium-containing material may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a semiconductor processing chamber. The methods may include flowing effluents of the fluorine-containing precursor through apertures defined in a chamber component. The apertures may be coated with a catalytic material. The methods may include reducing a concentration of fluorine radicals in the plasma effluents with the catalytic material. The methods may also include delivering the plasma effluents to a processing region of the semiconductor processing chamber. A substrate having an exposed region of a germanium-containing material may be housed within the processing region. The methods may further include etching the germanium-containing material.

Germanium etching systems and methods

The present disclosure provides methods for forming horizontal gate-all-around (hGAA) structure devices. In one example, a method includes selectively and laterally etching a first group of sidewalls of a first layer in a multi-material layer, wherein the multi-material layer comprises repeating pairs of the first layer and a second layer, the first and the second layers having the first group and a second group of sidewalls respectively, the first group of sidewalls from the first layer exposed through openings defined in the multi-material layer and a group of inner spacers formed atop of the second group of sidewalls from the second layer, forming a recess from the first group of sidewalls of the first layer and defining a vertical wall inward from an outer vertical surface of the inner spacer formed atop of the second layers, and forming an epi-silicon layer from the recess of the first layer.

Method for fabricating junctions and spacers for horizontal gate all around devices

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San Jose, CA, United States of America

Dimitri R Kioussis