Advanced Micro Devices Corporation

The University of Texas System

Ncr Corporation

Texas Instruments Corporation

National University of Singapore

Other

Agency for Science, Technology and Research

Novellus Systems Incorporated

Mattson Technology, Inc

Interuniversitair Microelektronica Centrum (imec)

Dim-Lee Kwong

Mark I Gardner

H Jim Fulford

Jonghan Kim

Giwan Yoon

Fred N Hause

Derryl D Allman

Liang-Kai Han

Jiang Yan

Derick J Wristers

Charles E May

Frederick N Hause

Hong Yu

Robert M Wallace

Glen D Wilk

Steven S Lee

Jorge Adrian Kittl

Guo-Qiang Patrick Lo

Ming Li

Mingbin Yu

Lakshmi Kanta Bera

HongYu Yu

Qingxin Zhang

Shiyang Zhu

Serge Biesemans

Chunxiang Zhu

Dirk J Wristers

Robert K Evans

Steven D Marcus

Jagar Singh

John A Bloom

Bruce T Acker

Jeff Gelpey

Mark Anthony

Li Mingfu

Chen JingDe

Sungjoo Lee

Jingde Chen

Ming-Fu Li

The wafer arrangement () provided comprises a first wafer (), which comprises an integrated circuit and a recess (). The wafer arrangement further comprises a portion of a second wafer (), which comprises a carrier portion and a protrusion (), the protrusion comprising an active component or actively controlled component () such as a MEMS component, wherein the portion of the second wafer () is coupled to the first wafer () such that the protrusion () is received in the recess (). The invention provides a mechanism for accurately aligning an active component () on the second wafer () with components on the first wafer (), such as photonic, electronic or optical components.

Wafer arrangement and a method for manufacturing the wafer arrangement

This invention relates to a semiconductor device making use of a highly thermal robust metal electrode as gate material. In particular, the development of Hafnium Nitride as a metal gate electrode (or a part of the metal gate stack) is taught and its manufacturing steps of fabrication with different embodiments are shown.

Thermal robust semiconductor device using HfN as metal gate electrode and the manufacturing process thereof

Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and semiconductor. In particular, an alloy of nickel-ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting nickel-ytterbium-silicon gate electrode has a work function of about 4.22 eV.

Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET

A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi) for source and drain is presented. The fabrication of YbSiis compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSifabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

Schottky barrier source/drain n-mosfet using ytterbium silicide

An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride. Alternatively, both nitride and a different high dielectric constant material may be used so that a three-layer dielectric is formed.

Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance

An integrated circuit capacitor comprising a high permittivity dielectric and a method of forming the same are disclosed herein. In one embodiment, this capacitor may be used as a DRAM storage cell. For example, a DRAM storage node electrode may be formed of polysilicon. An ultrathin oxynitride passivation layer (e.g. less than 1 nm) is formed on this electrode by exposure of the substrate to NO. A tantalum pentoxide layer is formed over layer , followed by a cell plate . Passivation layer allows electrode to resist oxidation during deposition of layer , thus preventing formation of an interfacial oxide layer. A passivation layer formed by this method may typically be deposited with shorter exposure times and lower temperatures than nitride passivation layers.

High charge storage density integrated circuit capacitor

An oxynitride film on the surface of a silicon or silicon germanium substrate is described where film is substantially an oxide film at the film oxide interface, and the nitrogen content of the film increases with the distance away from the substrate. The film is made by a process of rapidly processing a clean silicon wafer in an atmosphere of a nitrogen containing gas containing a very small percentage of oxygen containing gas.

Silicon oxynitride film

An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate dielectric layer on the substrate and forming a gate electrode on the gate dielectric layer with a lower surface, a midpoint, and a quantity of p-type impurity. A quantity of nitrogen is introduced into the gate electrode whereby the quantity nitrogen has a peak concentration proximate the lower surface. A quantity of germanium is introduced into the gate electrode and first and second source/drain regions are formed in the substrate. The method enables simultaneous formation of n-channel and p-channel gate electrodes with work functions tailored for both types of devices.

CMOS transistor design for shared N&plus;/P&plus; electrode with enhanced device performance

The present invention is directed to a semiconductor device having an ultra thin, reliable gate dielectric and a method for making same. In one illustrative embodiment, the present method comprises forming a first layer of nitrogen doped silicon dioxide above a semiconducting substrate, reducing the thickness of the first layer, forming a second layer comprised of a material having a dielectric constant greater than seven above the first layer of silicon dioxide. The method further comprises forming a third layer comprised of a gate conductor material above the second layer, and patterning the first, second and third layers to define a gate conductor and a composite gate dielectric comprised of the first and second layers, and forming at least one source/drain region. The semiconductor device has a composite gate dielectric comprised of a first process layer comprised of a nitrogen doped oxide and a second process layer comprised of a material having a dielectric constant greater than seven. The device further comprises a gate conductor positioned above the composite gate dielectric, and at least one source/drain region formed in the substrate.

Method of forming ultra thin gate dielectric for high performance semiconductor devices

A dense and stable dielectric layer of silicon nitride and silicon dioxide suitable for use in transistors of ULSI circuits is fabricated by a high pressure process in which a nitride layer is first formed on a surface of a silicon substrate and then a silicon dioxide layer is formed on the silicon surface under the nitride layer. By placing the nitride layer above the silicon dioxide and next to a doped polysilicon gate, diffusion of dopant ions such as boron from the gate into the silicon dioxide is reduced. As semiconductor devices are scaled down, the thermal budget required for the process steps is reduced.

Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology

Semiconductor devices having a metal gate electrode and a titanium or tantalum nitride gate dielectric barrier layer and processes for fabricating such devices are provided. The use of a metal gate electrode along with a titanium or tantalum nitride gate dielectric barrier layer can, for example, provide a highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.

Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.

Semiconductor topography employing a nitrogenated shallow trench isolation structure

An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.

High K integration of gate dielectric with integrated spacer formation for high speed CMOS

A process for fabricating a gate dielectric stack of a MOS transistor. A native oxide film is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then deposited on the native oxide film. A final dielectric film is then formed on the silicon nitride film. A dielectric constant of the final dielectric film is in the range of approximately 20-200. The substrate is then annealed in an inert ambient to produce the gate dielectric stack. An equivalent silicon dioxide thickness of the dielectric stack is typically in the range of approximately 5-20 angstroms whereby a gate dielectric stack suitable for use in deep sub-micron transistor is fabricated with a film thickness substantially in excess of an electrically equivalent silicon dioxide film. A suitable material for the final dielectric film includes oxides comprising oxygen and an element such as beryllium, magnesium, calcium, zirconium, titanium, or tantalum.

Method of making gate dielectric for sub-half micron MOS transistors

An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and especially in small silicide formation areas. The higher pressure helps ensure thermal contact of heated, flowing gas across relatively small geometries in which silicide is to be formed. Substantial metal silicide formation can occur at the higher pressures even under relatively lower temperature conditions. The lower temperature process helps ensure that pre-existing implant regions remain at their initial position. The present metal silicide process and lower temperature anneal is therefore well suited to avoid impurity migration problems such as, for example, threshold skew, parasitic junction capacitance enhancement, and gate oxide degradation.

Method for forming metal silicide on a semiconductor surface with

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Austin, TX, United States of America

Dim-Lee Kwong