Intel Corporation

Dilan Seneviratne

Aleksandar Aleksov

Srinivas V Pietambaram

Brandon C Marin

Yonggang Li

Praneeth Kumar Akkinepally

Frank Truong

Rahul N Manepalli

Whitney Michael Bryks

Sashi S Kandanur

Ching-Ping Janet Shen

Ravindranadh T Eluri

Kristof Darmawikarta

Robert Alan May

Sri Ranga Sai Boyapati

Jeremy D Ecton

Javier Soto Gonzalez

Shivasubramanian Balasubramanian

Shruti Rajeev Jaywant

Deepak Arora

Liwen Jin

Rajat Goyal

Kyu Oh Lee

Andrew James Brown

Charan K Gurumurthy

Hiroki Tanaka

Pramod Malatkar

Steve S Cho

Daniel N Sobieski

Nadine L Dabby

Yosuke Kanaoka

Jung Kyu Han

Jesse Jones

Srinivas Venkata Ramanuja Pietambaram

Thomas Heaton

Jieying Kong

Ali Lehaf

Ravi Shankar

Aritra Dhar

Bainye Francoise Angoua

Kristof Darmawaikarta

Jon M Williams

Adel A Elsherbini

Shawna M Liff

Robert L Sankman

Mauro J Kobrinsky

Ebrahim Andideh

Islam A Salama

Rahul Jain

Joshua Heppner

Vivek Raghunathan

Gang Duan

Houssam Jomaa

Wei-Lun Kane Jen

Braxton L Lathrop

Richard J Harries

Drew W Delaney

Meizi Jiao

Kyle Yazzie

Sameer Paital

Darko Grujicic

Oscar Ojeda

Tatyana N Andryushchenko

Charavana K Gurumurthy

Rengarajan Shanmugam

Roy Dittler

Vinodhkumar Raghunathan

Amruthavalli Palla Alur

David W Staines

Alejandro X Levander

Naga Sivakumar Yagnamurthy

Sarah Blythe

Trina Ghosh Dastidar

Rafiqul Islam

Ala Omer

Chi-Mon Chen

Albert S Lopez

Sirisha Chava

James C Meyer

Padam Jain

Melissa Wette

Patrick Quach

Junxin Wang

Xuefei Wan

Son V Nguyen

David B Lampner

Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.

Optical waveguide formed within in a glass layer

Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Embedded die microelectronic device with molded component

A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than s second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.

Semiconductor packages with embedded interconnects

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Surface finishes with low RBTV for fine and mixed bump pitch architectures

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

Glass dielectric layer with patterning

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

Microelectronic assemblies having conductive structures with different thicknesses

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

Selective deposition of embedded thin-film resistors for semiconductor packaging

A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 &#x3bc;m in thickness, and a second electrode is over the cured PID.

Ultra-thin dielectric films using photo up-conversion for applications in substrate manufacturing and integrating passives

A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.

Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same

A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.

Fabricating an RF filter on a semiconductor package using selective seeding

Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.

Dielectric film with pressure sensitive microcapsules of adhesion promoter

Surface finishes with low rBTV for fine and mixed bump pitch architectures

A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than a second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.

Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

Package-integrated vertical capacitors and methods of assembling same

Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Growing community of inventors

Chandler, AZ, United States of America

Dilan Seneviratne