Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies Richmond, LP

Infineon Technologies North America Corp.

Dietrich Widmann

Gerhard Enders

Lothar Risch

Georg Tempel

Thomas Schulz

Martin Kerber

Matthias Ilg

Wolfgang Hoenlein

Hans-Jorg Pfleiderer

Reiner Sigusch

Christoph Friedrich

Volker Lehmann

Reinhard J Stengl

Hermann Wendt

Martin Franosch

Hans Reisinger

Karl-Ulrich Stein

Helmut Klose

Andreas Grassmann

Heiner Herbst

Rainer Pforr

Justus Kuhn

Michael Schittenhelm

Hanno Melzner

Herbert Schaefer

Jochen M&uuml;ller

Gerrit Lange

Jens L&uuml;pke

Uwe Griesinger

G&uuml;nther Czech

Carsten F&uuml;lber

Johann Binder

Rainer K&auml;smaier

Peter Pochm&uuml;ller

Armin Wieder

Layers are patterned with a lithography method during the fabrication of integrated circuits. A mask, which may be reflective or transmissive, for carrying out the method. The photosensitive layers are exposed to radiation that is emitted by a radiation source. The radiation lies in the extreme ultraviolet region and is guided via the mask onto the photosensitive layers.

Lithography method and lithography mask

The invention relates to a phase shift mask for lithographically producing small structures at the limit of a resolution that is predetermined by the wavelength of the exposure radiation. The phase shift mask has first regions A and second regions B that effect a phase-shift relative to the first regions. The second regions are arranged beside the first regions for producing a sudden phase shift along the boundaries between the first and the second regions. Individual first regions touch one another via corners at points, at which the second regions also touch one another via corners. The result is that the boundaries between first and second regions merge at these points and these points are opaque to the radiation. The invention makes it possible to expose extremely small contact holes with just a single exposure and thus leads to a reduction of costs in the fabrication of integrated semiconductor circuits.

Contact hole fabrication with the aid of mutually crossing sudden phase shift edges of a single phase shift mask

An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Field-effect-controlled transistor and method for fabricating the transistor

A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

Double gated transistor

A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

Static random access memory (SRAM)

A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor substrate, includes forming a trench in a layer applied to the substrate. An electrically conductive layer for the second capacitor electrode is deposited inside the trench and at least regionally conformally with side walls thereof. An auxiliary layer acting as a space-holder for the dielectric is conformally deposited inside the trench and on the electrically conductive layer for the second capacitor electrode. An electrically conductive layer for the first capacitor electrode is conformally deposited inside the trench and on the auxiliary layer. The auxiliary layer is at least partially removed to expose a hollow layer in at least a partial region between the two electrically conductive layers for the first and second capacitor electrodes. The dielectric is deposited into the exposed hollow layer between the two electrically conductive layers. A semiconductor memory device and a method for producing the device include producing the capacitor after production of the transistor and metallizing layers associated therewith for connection of the word and bit lines, in a configuration projecting upward from the plane; placing the capacitor in a trench formed inside a contact metallizing layer for the second electrode terminal of the transistor; and setting a depth of the trench to be equivalent to a layer thickness of the metallizing layer.

Method for producing a semiconductor memory device with a multiplicity of memory cells

A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched onto the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.

CMOS circuit with all-around dielectrically insulated source-drain regions

A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

Method for forming a high surface area trench capacitor

A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.

Memory cell having trench capacitor and vertical, dual-gated transistor

Method for producing a capacitor

A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched into the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.

Process for manufacturing a CMOS circuit with all-around dielectrically

For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Method for manufacturing a capacitor for a semiconductor arrangement

A capacitor in a semiconductor configuration, especially a DRAM, includes an electrode structure having a plurality of spaced-apart elements being electrically connected with a connecting structure and all including p-conductive material with a doping &gt;10.sup.10 cm.sup.-3. The elements of the electrode structure are either stacked or disposed side by side and may be cup-shaped. In a production process, a layer sequence of alternatingly one p.sup.- -doped and one p.sup.+ -doped layer is produced, which receives an opening through the use of anisotropic etching. At least in a peripheral region of the opening, a p.sup.+ -zone is created, which connects the layer sequence and forms the connecting structure. Next, the p.sup.- -doped layers are etched selectively to the p.sup.+ -doped layers, a capacitor dielectric is deposited, and a counterelectrode is produced.

Capacitor in a semiconductor configuration and process for its production

A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor substrate, includes forming a trench in a layer applied to the substrate. An electrically conductive layer for the second capacitor electrode is deposited inside the trench and at least regionally conformally with side walls thereof. An auxiliary layer acting as a space-holder for the dielectric is conformally deposited inside the trench and on the electrically conductive layer for the second capacitor electrode. An electrically conductive layer for the first capacitor electrode is conformally deposited inside the trench and on the auxiliary layer. The auxiliary layer is at least partial removed to expose a hollow layer in at least a partial region between the two electrically conductive layers for the first and second capacitor electrodes. The dielectric is deposited into the exposed hollow layer between the two electrically conductive layers. A semiconductor memory device and a method for producing the device include producing the capacitor after production of the transistor and metallizing layers associated therewith for connection of the word and bit lines, in a configuration projecting upward from the plane; placing the capacitor in a trench formed inside a contact metallizing layer for the second electrode terminal of the transistor; and setting a depth of the trench to be equivalent to a layer thickness of the metallizing layer.

Ferroelectric memory device and method for producing the device

Growing community of inventors

Unterhaching, Germany

Dietrich Widmann