Lsi Corporation

Dharmesh Kishor Tirthdasani

Romeshkumar Bharatkumar Mehta

Srinivasa Rao Kothamasu

Sathappan Palaniappan

Ravindra Bidnur

Debjit Roy Choudhury

Jean Jacob

Sajith Kizhakke Kalathil Achuthan Kutty

A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.

Power gated memory device with power state indication

A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

Method and apparatus for decreasing leakage power consumption in power gated memories

An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.

Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port

A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.

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Bengaluru, India

Dharmesh Kishor Tirthdasani