Altera Corporation

Dhananjay Srinivasa Raghavan

Paul J Tracy

Zunhang Yu Kasnavi

Jaydev Amit Shelat

Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.

Delay test circuitry

An integrated circuit is provided that includes testing circuitry for testing input-output circuits. The integrated circuit contains input-output circuits that each have associated input-output pins and input and output buffers. Each input-output circuit has associated features such as a weak pull-up feature, a voltage clamp diode feature, a bus hold feature, an open-drain feature, a differential input termination resistance feature, and a single-ended/differential mode selection feature. An input-output feature control register receives input-output circuit feature selection instructions. The feature selection instructions contain feature selection bits whose values determine which of the input-output circuit features are enabled in a set of input-output circuits for testing on the integrated circuit. The feature selection instructions can selectively enable one or more input-output circuit features in each input-output circuit. Different feature selection instructions can be loaded into the feature control register to systematically test the input-output circuit features.

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Campbell, CA, United States of America

Dhananjay Srinivasa Raghavan