Qualcomm Incorporated

Kyocera Wireless Corporation

Kyocera Corporation

Dhamim Packer Ali

Dhaval Kanubhai Patel

Sreenivasulu Reddy Chalamcharla

Yanru Li

Eugen Pirvu

Eric Taseski

Mamta Desai

Daison Davis Koola

Ashutosh Shrivastava

Alexander Gantman

Benish Babu

Yugandhar Narayana

Ruchi Parekh

Ajay Iyengar

Azzedine Touzni

Jian Zhang

Anushka Mihir Nabar

Justin Yongjin Kim

Leonard Widra

Santan Kumar

Rudhresh Kumar

Kedar Athawale

Eric Tallet

Maria Miranda

Cory David Feitelson

Bhargav Gurappadi

Venkata Vara Prasad Gorantla

Taara Nandakishore Ellala

Ashwani Kumar

Tom C Wang

Thirupathi Venkatarajan

Darshana Advani

Sha Liu

Dhaval Patel

Ashutosh Jagdish Shrivastava

A method of improving synchronization over a secure digital (SD) bus between an SD host and an SD client device is described. The method includes writing to a client event register to interrupt the SD host for an SD extended command. The method also includes triggering the SD host to issue the SD extended command to the SD client device over the SD bus in response to the SD client device writing to the client event register.

SDIO chip-to-chip interconnect protocol extension for slow devices and power savings

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the external component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

Boot time determination of calibration parameters for a component coupled to a system-on-chip

Various aspects include methods for implementing a reduced size firmware storage format on a computing device. Various aspects may include storing a first firmware description table to a first sector of a flash memory, in which the first firmware description table may define a first instance of a firmware including describing a first plurality of firmware images, storing the first plurality of firmware images to a first plurality of consecutive sectors, storing a second firmware description table to a second sector, in which the second firmware description table may define a second instance of the firmware including describing a second plurality of firmware images having a third plurality of firmware images, storing the third plurality of firmware images to a second plurality of consecutive sectors, and booting the computing device using the second firmware description table.

Partitioning flash and enabling flexible boot with image upgrade capabilities

Various aspects are described herein. In some aspects, the disclosure provides a method of enabling a multicore framework in a pre-boot environment for a system-on-chip (SoC) comprising a plurality of processors comprising a first processor and a second processor. The method includes initiating, by the first processor, bootup of the SoC into a pre-boot environment. The method further includes scheduling, by the first processor, execution of one or more boot-up tasks by a second processor. The method further includes executing, by the second processor, the one or more boot-up tasks in the pre-boot environment. The method further includes executing, by the first processor, one or more additional tasks in parallel with the second processor executing the one or more boot-up tasks.

Multicore framework for use in pre-boot environment of a system-on-chip

Various aspects are described herein. In some aspects, the disclosure provides a method for a system-on-chip (SoC) including one or more computing cores. The method includes providing a scheduler to schedule running of threads on the one or more computing cores in a pre-boot environment including a core thread configured to provide a plurality of services. The method further includes providing, by the scheduler, a first lock for the core thread. The method further includes initializing, by the core thread, one or more additional services separate from the plurality of services. The method further includes selectively allowing access to the plurality of services of the core thread to one or more additional threads based on a status of the first lock. The method further includes allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock.

Multithread framework for use in pre-boot environment of a system-on-chip

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of authenticating executable images in a system-on-chip (SoC), the method comprising: storing a plurality of executable images; storing, as separate from the plurality of executable images, a signed image of hashes comprising a plurality of hashes corresponding to the plurality of executable images and a first signature; authenticating the signed image of hashes based on the first signature; and using a first hash of the plurality of hashes to authenticate a first executable image of the plurality of executable images when the signed image of hashes passes authentication.

Collated multi-image check in system-on-chips

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.

Selectable boot CPU

Systems and methods are disclosed for providing stack overflow protection on a system on chip via a hardware write-once register. An exemplary embodiment of an system on chip comprises a hardware write-once register, a boot processor, and one or more processor subsystems. The boot processor is configured to execute a read only memory (ROM) image which initializes the hardware write-once register with a first numeric value in response to the system on chip being powered on. The one or more processor subsystems have an associated software image configured to use the first numeric value in the hardware write-once register as a stack canary value to combat stack overflow attacks.

Secure stack overflow protection via a hardware write-once register

Various aspects include methods for implementing a firmware patch infrastructure. Various aspects may include identifying a patchable object from a firmware source code image based on a symbol in the patchable object's name, generating a patchable firmware source code file by injecting a first call to the patchable object configured to call to an indirection table and a second call to the patchable object configure to execute the patchable object, building a patchable firmware source code image from a plurality of patchable firmware source code files including the patchable firmware source code file having the first call to the patchable object and the second call to the patchable object, and creating the indirection table including an entry for the first call from the patchable firmware source code image having an indication to implement the second call in the patchable firmware source code image.

Patch infrastructure for ROM firmware

A system and a method for power mode selection in a portable computing device is provided herein. The system and method may comprise operations for operating the portable computing device in a normal mode. The normal mode may utilize a plurality of memory banks within a volatile memory, such as a random access memory ('RAM'), where the memory banks are powered-up and operable to store data. The system and method may further identify a memory segment within the plurality of memory banks, store the memory segment as a stored memory segment (where the stored memory segment is operable to restore the memory segment), and power down the powered-up memory bank associated with the memory segment. Further aspects are described herein.

System and method for power mode selection in a computing device

A system and method for patching a boot sequence in a read-only memory. Patch instances are provided in an addressable memory. The patch instances are initially empty. The read-only memory includes a process that dynamically vectors to identified locations in a set of addressable memory locations in the addressable memory. Thereafter, the process returns to the next subsequent instruction following the patch instance. As corrections are required, the one or more patch instances are populated with one or more respective patches. The boot sequence is modified by inserting one or more patch indicators located where patches might need to be applied after a system-on-chip (SoC) is embodied in firmware. The patches, when defined, are populated with at least an encoded instruction type and an address. Accordingly, a patch is enabled in no more than three words.

System and method for modifying a sequence of instructions in a read-only memory of a computing device

Methods, systems and devices are provided for configuring a read-write memory device with a data image. The method includes determining a data image distribution based on a virtual block size of a series of virtual blocks designated for the read-write memory device. The data image is divided into one or more data image portions, wherein a virtual boundary code is appended to at least one of the data image portions. The data image portions are stored in respective virtual blocks of the series of virtual blocks, skipping over any bad block within the read-write memory device, even between the virtual blocks.

Virtual boundary codes in a data image of a read-write memory device

A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.

Apparatus, system and method for autonomous recovery from failures during system characterization on an environment with restricted resources

Persistent files stored in non-XIP flash memory are accessed during operation of an electronic device. During execution of application code on the device, the persistent files are accessed using an access directory such as a look-up table. The access directory provides information that allows an application or other software code running on the processor of the device to locate and access a persistent file within a non-XIP flash memory device where the non-XIP flash memory device may include bad blocks. During creation of the access directory, locations of the bad blocks in the device are identified and recorded. Files are accessed from the non-XIP flash memory device by reading from file start locations identified in the access directory while accounting for bad blocks identified in the bad block data of the access directory.

Growing community of inventors

San Diego, CA, United States of America

Dhamim Packer Ali