Siemens Aktiengesellschaft

Dezsoe Takacs

Ulrich Schwabe

Erwin P Jacobs

The invention relates to a MNOS memory cell arrangement in VLSI (very large scale integration) technology comprised of a multi-layer gate insulating layer covering a surface of a semiconductor body in the region between the source and drain zones. In order to avoid breakdowns at the source and drain zone edges before an erasure voltage is attained, the gate electrode is split into two electrodes, which can be operated in different ways and which are superimposed on upon another. These gate electrodes are connected via self-aligned, overlapped contacts. This arrangement resolves 'short channel erasure', even in the case of VLSI technology. The invention can be applied as required to MNOS EEPROM memory devices.

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Munich, Germany

Dezsoe Takacs