Globalfoundries U.S. Inc.

Globalfoundries Inc.

Dewei Xu

Sunil Kumar Singh

Eric D Hunt-Schroeder

Nicholas A Polomoff

Seung-Yeop Kook

Roderick Alan Augur

Matthew Thomas Herrick

Zhuojie Wu

Dirk Breuer

Teck Jung Tang

Bernhard J Wunder

Devender

M Golam Faruk

Siva R Dangeti

Alamgir M Arif

Daniel Smith

A structure includes a through semiconductor via (TSV) in a semiconductor substrate, and a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate. A plurality of discontinuous air gaps is in the semiconductor substrate extending away from the dielectric liner, e.g., radially. The discontinuous air gaps reduce the parasitic coupling capacitance and relieve stress in the semiconductor substrate.

Structure with air gaps extending from dielectric liner around through semicondcutor via

Embodiments of the disclosure provide an integrated circuit (IC) structure. With capacitor electrodes in different ILD layers. The structure includes a first inter-level dielectric (ILD) layer having a top surface, a first vertical electrode within the first ILD layer, a capacitor dielectric film on a top surface of the first vertical electrode, a second ILD layer over the first ILD layer, and a second vertical electrode within the second ILD layer and on the capacitor dielectric film. The capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode.

Integrated circuit structure with capacitor electrodes in different ILD layers, and related methods

Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

Cascaded sensing circuits for detecting and monitoring cracks in an integrated circuit

Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor.

Capacitor structure for integrated circuit and related methods

Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.

Capacitor structure for integrated circuit, and related methods

Embodiments of the disclosure provide a system for detecting and monitoring a crack in an integrated circuit (IC), including: at least one electrically conductive perimeter line (PLINE) extending about, and electrically isolated from, a protective structure formed in an inactive region of the IC, wherein an active region of the IC is enclosed within the protective structure; a circuit for sensing a change in an electrical characteristic of the at least one PLINE, the change in the electrical characteristic indicating a presence of a crack in the inactive region of the IC; and a connecting structure for electrically coupling each PLINE to the sensing circuit.

Crack detecting and monitoring system for an integrated circuit

The present disclosure describes a method or forming vertical natural capacitor (VNCAP) and the resulting device. The method includes applying a patterned mask over an insulation layer. The method includes forming using the patterned mask, a dielectric trench in the insulation layer. The method includes depositing a high dielectric constant k (high k) layer in the dielectric trench. The method includes forming a first trench and a second trench in the high k dielectric layer. The high k dielectric layer is disposed between the first trench and the second trench. The method includes depositing metal in the first trench and the second trench.

Method of forming high performance vertical natural capacitor (VNCAP)

Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

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Clifton Park, NY, United States of America

Dewei Xu