Sun Microsystems, Inc.

Oracle America, Inc.

Deviprasad Malladi

Vadim Gektin

Shahid S Ansari

Eric L Bogatin

Bidyut Kanti Sen

Steven R Boyle

Nagaraj P Mitty

Hanxi Chen

Stefan Rusu

Alan C Rogers

Ron Zhang

Ehsan Ettehadieh

David Hockanson

Mario J Lee

Douglas W Forehand

Renukanthan Raman

Clayton L Yee

George C Zacharisen

Christopher Furman

Herbert E LeCornu

Bahram Zand

Jean Kahahane

Lee Frederick Hanson

A multi-surface compliant heat removal process that includes identifying components to share a heat rejecting device; applying non-adhesive film to the components; identifying a primary component of the components; and applying phase change material on each of the components, other than the primary component. The phase change material is placed on top of the non-adhesive film. The process also includes placing the heat rejecting device on the corresponding components and removing the heat rejecting device from the corresponding components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device; removing the non-adhesive film from the heat rejecting device; placing a heatsink-attach thermal interface material on the components; and placing the heat rejecting device on the corresponding components.

Optimized lid attach process for thermal management and multi-surface compliant heat removal

A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device, applying non-adhesive film to the one or more components, identifying a primary component of the one or more components, and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device, removing the non-adhesive film from the heat rejecting device, placing a heatsink-attach thermal interface material on the one or more components, and placing the heat rejecting device on the corresponding one or more components.

A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.

Package lid or heat spreader for microprocessor packages

An electromagnetic shielding structure is provided for a microprocessor or other electronic device that emits electromagnetic radiation. The structure includes a heat sink with an integrally formed depending skirt, and a conductive, compressible polymer is applied to a bottom surface of the skirt. The bottom surface mounts against a socket carried on a circuit board and is electrically coupled to a ground plane of the circuit board. The socket substantially surrounds the microprocessor in at least two dimensions (e.g. length and width). A shielding structure is formed at least partly by the heat sink, the socket and the ground plane.

EMI shielding apparatus

Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions. In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.

Apparatus and methods for enhancing thermal performance of integrated circuit packages

In an embodiment, an apparatus for enhancing a thermal match between portions of a semiconductor device is disclosed. The apparatus includes a die and a heat spreader. The heat spreader is in thermal contact with the die. The heat spreader has a center portion and a perimeter portion. The center portion and the perimeter portions are structurally coupled to each other. In another embodiment, the perimeter portion of the heat spreader is selected from material with a lower CTE than the material for the center portion of the heat spreader.

Multi-material heat spreader

A method for performing electrical acceptance tests on a sub-system including a test substrate, a microprocessor and one or more associated computer components, such as SRAM, DRAM and ROM. A pin grid array, ball grid array, line grid array or equivalent test connector system is provided that allows direct addressing of selected circuits of the microprocessor and of each associated component. The microprocessor plus substrate are first tested together. If this test is successful, the associated components are then added, preferably one at a time, and the new sub-system is tested. If a particular sub-system fails a test, the cause(s) of failure can be isolated and removed, where possible, and the modified sub-system can be retested.

Component level, CPU-testable, multi-chip package using grid arrays

A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Efficient device debug system

A method for reducing soft error rates in semiconductor devices includes adding an isotopically enriched B compound during the manufacture of a semiconductor device. Such isotopically enriched B compounds include orthoborates (BOR ), acyl borates (B(OCOR) ), peroxo borates (OOR) , boronic acids (RB(OH) ), boron halides, boron hydrides, inorganic boranes, amine boranes, aminoboranes, carboranes, and borazines, where R is an alkyl group. Disclosed uses include adding between 1% to 100% of the isotopically enriched B compound to an underfill material in flip-chip assembly; adding between 1% to 100% of the isotopically enriched B compound to an encapsulent; and adding between 1% to 100% of the isotopically enriched B compound to an adhesive.

Method for reducing soft error rates in semiconductor devices

A method and apparatus for packaging an electronic device, such as an integrated circuit chip ( ), includes an intermediate device carrier ( ) with a substantially planar upper surface ( ) and a plurality of bonding pads ( ) for coupling the carrier to the integrated circuit chip. A ceramic ring ( ) is attached to the upper surface of the device carrier and a thermally conductive cover plate ( ) is attached to the ceramic ring to form an inner cavity for receiving the chip therein. The ceramic ring comprises a material with a coefficient of thermal expansion substantially similar to or as the same as the device carrier to minimize stress therebetween during thermal expansion or contraction of the package device. The thermally conductive cover plate provides a path for dissipating heat generated during electrical operations of the chip.

Device and method for packaging an electronic device

A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Efficient debug package design

An integrated circuit package with heat slug is disclosed. The heat slug is thermally coupled to one or more semiconductor die using a single layer of high conductivity adhesive. The assembly process of this invention includes the steps of initially attaching a temporary heat slug to the back side of a package body, to which one or more semiconductor die are attached. The semiconductor die are then electrically connected to the package body and encapsulated to maintain fixed positions within the package cavity. The temporary heat slug is then moved and a final heat slug is attached to the package body and the back side of the one or more semiconductor dies utilizing a single layer of high conductivity adhesive. The package is compact, has reduced complexity, and is inexpensive to manufacture.

Integrated circuit package and method

A structure and method for controlling the junction temperature of a semiconductor chip in an electronic system. A temperature sensing device and the chip whose junction temperature is to be monitored are located adjacent to one another on the same interconnect structure. A thermally conductive lid can also be attached to the interconnect structure, thereby enclosing the temperature sensing device and the chip within in a closed cavity. Dedicated pins extend from the temperature sensing device through the interconnect structure, for connection to a temperature control circuit. By locating the temperature sensing device on the same interconnect structure as the chip, and within a common enclosure, the temperature sensed by the temperature sensing device is an accurate representation of the actual junction temperature of the chip. By obtaining an improved reading of the actual junction temperature, the operation of the temperature control circuit can be optimized.

Integrated junction temperature sensor/package design and method of

Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ('FIB'). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or other conductive bond material. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

Method for direct attachment of an on-chip bypass capacitor in an

Because of space limitations, a small heat sink and a fan (of about 2'.times.2'.times.1/2' size) is used to cool to below 105.degree. C. (at an ambient temperature of about 40.degree. C.) a CPU chip (of about 16 mm.times.16 mm size) which uses about 30 watts current and is mounted on a motherboard of considerably larger size. A heat transferring thermostrate washer covers the chip and a pad covers the washer. Soldered to the pad is a square heat slug. Studs extend upward from the slug. The studs fit through holes in the base of the heat sink. The heat sink is of the type having plural rectangular cross-section fins extending upwardly from the base. Above the heat sink is a fan attached to the motherboard by screws at its four corners extending through heat slug and into the motherboard.

Growing community of inventors

Fremont, CA, United States of America

Deviprasad Malladi