Infineon Technologies Ag

Siced Electronics Development Gmbh & Co Kg

Infineon Technologies Austria Ag

Siemens Aktiengesellschaft

Sciced Electronics Development Gmbh & Co. Kg

Dethard Peters

Ralf Siemieniec

Romain Esteve

Wolfgang Bergner

Thomas Aichinger

Roland Rupp

Rudolf Elpelt

Caspar Leendertz

Thomas Basler

Bernd Zippelius

Peter Friedrichs

Daniel Kueck

Michael Hell

Shiqin Niu

Paul Ellinghaus

Jens Peter Konrath

Reinhold Sch&ouml;rner

Hans-Joachim Schulze

Anton Mauder

Dietrich Stephani

Andreas Huerner

Florian Grasse

Konrad Schraml

Tomas Manuel Reiter

Frank Wolter

Jochen Hilsenbeck

Reinhold Schoerner

Gerald Unegg

Sandeep Walia

Sascha Axel Baier

Victorina Poenariu

Gerald Reinwald

Edward Fuergut

Martin Gruber

Joachim Weyers

Ravi Keshav Joshi

Michael Treu

Stephan Pindl

Juergen Steinbrenner

Wolfgang Jantscher

Wolfgang Scholz

Larissa Wehrhahn-Kilian

David Kammerlander

Hans-Guenter Eckel

Reinhold Schörner

Guang Zeng

Christian Stahlhut

Jan Fuhrmann

Christian Strenger

Michael Glavanovics

Andreas Hürner

Markus Sievers

Josef Schaetz

Florian Stoermer

Paul Sochor

Karlheinz Feldrapp

Paul Salmen

Tobias Schmidutz

Vice Sodan

In an example, a silicon carbide device includes a silicon carbide body. The silicon carbide body includes a central region and a peripheral region surrounding the central region. The central region includes a source region of a first conductivity type. The peripheral region includes a doped region of a second conductivity type. A stripe-shaped gate electrode extends through the central region and into the peripheral region. A contiguous source metallization is formed on the central region and on an inner portion of the peripheral region. The contiguous source metallization and the source region form a first ohmic contact in the central region. The contiguous source metallization and the doped region form a second ohmic contact in the peripheral region.

Silicon carbide device with stripe-shaped gate electrode and source metallization

A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

Vertical power semiconductor device including silicon carbide (sic) semiconductor body

An apparatus includes a junction termination edge, a unipolar power transistor, and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate, and part of the junction termination edge. The capacitor has a p-n junction. The RC snubber has a poly silicon resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

RC snubber with poly silicon resistor and capacitor formed from junction termination edge

A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

Silicon carbide device with a stripe-shaped trench gate structure

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

Dual mode current and temperature sensing for SiC devices

A transistor cell includes a gate electrode and a source region of a first conductivity type. A drain/drift region is formed in a silicon carbide body. A buried region of the second conductivity type and the drain/drift region form a pn junction. The buried region and a well region form a unipolar junction. A mean net dopant density Nof the buried region is higher than a mean net dopant density Nof the well region. A first clamp region of the first conductivity type extends into the well region. A first low-resistive ohmic path electrically connects the first clamp region and the gate electrode. A second clamp region of the first conductivity type extends into the well region. A second low-resistive ohmic path electrically connects the second clamp region and the source region.

Silicon carbide device with transistor cell and clamp regions in a well region

A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

Method of producing a silicon carbide device with a trench gate

A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

Silicon carbide device and method for forming a silicon carbide device

A device is provided that includes a power transistor and an overcurrent detection logic. The overcurrent detection logic has a first stable state providing a first signal level on a status output terminal and a second stable state providing a second signal level on the status output terminal. The overcurrent detection logic changes from the first stable state to the second stable state in response to detecting that a current through the power transistor exceeds a current limit. The overcurrent detection logic remains in the second state when the current through the transistor drops below the limit after exceeding the current limit.

Device including power transistor and overcurrent detection logic and method for operating a power transistor

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

SiC device having a dual mode sense terminal, electronic systems for current and temperature sensing, and methods of current and temperature sensing

A power semiconductor device includes: a semiconductor body having a front side and a backside and configured to conduct a load current between the front side and the backside; and a plurality of control cells configured to control the load current. Each control cell is at least partially included in the semiconductor body at the front side and includes a gate electrode that is electrically insulated from the semiconductor body by a gate insulation layer. The gate insulation layer is or includes a first boron nitride layer.

Power semiconductor device and method

A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

Silicon carbide field-effect transistor including shielding areas

In an example, a semiconductor device includes an insulated gate transistor cell, a first region (e.g., a drain region and/or a drift region), a cathode region, a second region (e.g., an anode region and/or a separation region), and a source electrode. The insulated gate transistor cell includes a source region and a gate electrode. The source region and the cathode region are in a silicon carbide body. The gate electrode and the cathode region are electrically connected. The cathode region, the source region, and the first region have a first conductivity type. The second region has a second conductivity type and is between the cathode region and the first region. The source electrode and the source region are electrically connected. The source electrode and the second region are in contact with each other. A rectifying junction is electrically coupled between the source electrode and the cathode region.

Semiconductor device with insulated gate transistor cell and rectifying junction

An apparatus includes a unipolar power transistor and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate. The capacitor has a p-n junction. The RC snubber has a resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

RC snubber

A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

Silicon carbide device with trench gate

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Hoechstadt, Germany

Dethard Peters