Lsi Logic Corporation

Derryl J Allman

Peter McGrath

Shiqun Gu

Charles E May

David T Price

Robi Banerjee

Shioun Gu

A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Method of forming a low k polymer E-beam printable mechanical support

An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.

Semiconductor chip with borderless contact that avoids well leakage

Low k polymer E-beam printable mechanical support

Method for preventing borderless contact to well leakage

A semiconductor device wherein Si&mdash;Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application and exposure to define where a HBT device will be placed. Plasma etching the Silicon dioxide layer to define an undercut, epitaxially growing an Si&mdash;Ge layer and a Silicon layer, and continuing manufacture to form one or more bipolar and CMOS devices and define interconnect and passivation.

Implementation of Si-Ge HBT with CMOS process

A semiconductor device wherein some parts of a circuit are disposed on Si&mdash;Ge regions and others are implemented in Silicon substrate regions of the chip. The Si&mdash;Ge region provides that carrier flow is forced to the surface channel region which helps reduce short channel effects. A method of making such a semiconductor device is also provided and includes steps of forming a thermal oxide layer on a Silicon substrate, masking at least a portion of the thermal oxide layer, removing at least a portion of the thermal oxide layer in order to expose a portion of the Silicon substrate, epitaxially growing an Si&mdash;Ge layer on the exposed portion of the Silicon substrate, epitaxially growing a Silicon layer on the Si&mdash;Ge layer, and continuing manufacture of the device by forming a circuit on the Si&mdash;Ge regions and non-Si&mdash;Ge regions of the semiconductor device.

Growing community of inventors

Camas, WA, United States of America

Derryl J Allman