Lsi Logic Corporation

Hyundai Electronics America, Inc.

Lsi Corporation

Other

Nantero, Inc.

Lsi Lgoic Corporation

Derryl D J Allman

Kenneth P Fuchs

John W Gregory

Gayle W Miller

Hemanshu D Bhatt

Samuel C Gioia

Charles E May

Ponce Saopraseuth

Verne C Hornbeck

David T Price

David Pritchard

Peter Austin Burke

Byung-Sung Kwak

Sey-Shing Sun

David W Daniel

Verne C Hornback

Jan Fure

Dim Lee Kwong

Jeffrey F Hanson

Nabil Mansour

James R Hightower

Phonesavanh Saopraseuth

Claude Louis Bertin

Thomas Rueckes

Shiqun Gu

Todd A Randazzo

Bruce Joseph Whitefield

John J Seliskar

James P Yakura

Newell E Chiesl

Charles W Jurgensen

Brian R Lee

John Q Walker

Curtis C Hainds

Sam Gu

Steve Reder

Brian Bystedt

A method of forming a carbon nanotube fuse by depositing a carbon nanotube layer, then depositing a cap layer directly over the carbon nanotube layer. The cap layer is formed of a material that has an insufficient amount of oxygen to significantly oxidize the carbon nanotube layer under operating conditions, and is otherwise sufficiently robust to protect the carbon nanotube layer from oxygen and plasmas. A photoresist layer is formed over the cap layer, and the photoresist layer is patterned to define a desired size of fuse. Both the cap layer and the carbon nanotube layer are completely etched, without removing the photoresist layer, to define the fuse having two ends in the carbon nanotube layer. Just the cap layer is etched, without removing the photoresist layer, so as to reduce the cap layer by a desired amount at the edges of the cap layer under the photoresist layer, without damaging the carbon nanotube layer. The photoresist layer is removed, and electrically conductive contacts are formed on each of the two ends of the fuse.

Nanotube fuse structure

A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Method for redirecting void diffusion away from vias in an integrated circuit design

A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

Method and apparatus for diverting void diffusion in integrated circuit conductors

An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.

Integrated circuit with inductor having horizontal magnetic flux lines

A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design

A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

Method of forming a metal-insulator-metal capacitor in an interconnect cavity

An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

Local interconnect for integrated circuit

A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.

Bond pad design

A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Capacitor with stoichiometrically adjusted dielectric and method of fabricating same

A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels. Furthermore, by allowing these local electrical interconnections to be produced during the same manufacturing step as the macro elements of the integrated circuit, the method of the present invention tends to reduce the number of steps required to produce an integrated circuit.

Local interconnect

A process for forming a conductive via in an integrated circuit structure that includes a first dielectric layer overlying a first conductive layer. A via cavity is formed in the first dielectric layer, which exposes the first conductive layer. A titanium nitride liner layer is formed in the via cavity, and the titanium nitride liner layer is exposed to an isotropic plasma containing hydrogen ions, thereby densifying the liner layer. A second conductive layer is formed adjacent the titanium nitride liner layer in the via cavity, which second conductive layer substantially fills the via cavity to form the conductive via. The via cavity is selectively etched with a hydrogen containing plasma prior to forming the titanium nitride liner layer. The plasma etch at least partially removes residue in the bottom of the via cavity, including carbon and oxygen.

Plasma treatment system

A graded index of refraction optical waveguide is formed in interlayer dielectric material located above a substrate an integrated circuit-like structure. The waveguide includes a refractive layer of optically transmissive material surrounding a core of optically transmissive material within a trench in the dielectric material. The material of the core has a higher index of refraction than the refractive layer and the material of the refractive layer has a higher index of refraction than the dielectric material. More than one refractive layer may also be formed in the trench, with the inner refractive layer having an index of refraction higher than the outer refractive layer and less than the core.

On-chip graded index of refraction optical waveguide and damascene method of fabricating the same

A bonding pad for an integrated circuit, having a conductive base layer. The conductive base layer has slots formed in it, where the slots extend completely through the conductive base layer. An insulating layer is disposed on top of the conductive base layer. The insulating layer protrudes into the slots of the conductive base layer. The insulating layer also includes a low k material. A conductive top layer is disposed on top of the insulating layer.

Method for forming a bonding pad on a substrate

Growing community of inventors

Camas, WA, United States of America

Derryl D J Allman