Samsung Electronics Co., Ltd.

Deok Han Bae

Myung Yoon Um

Ju Hun Park

In Yeal Lee

Sang Young Kim

Hyun Jin Kim

Jin-Wook Kim

Hyung Jong Lee

Byung Chan Ryu

Da Un Jeon

Yoon Young Jung

Jin Wook Kim

Ju Youn Kim

Yu Ri Lee

Sung Min Kim

Jong Ho You

Won Cheol Jeong

Jong Mil Youn

Sun Me Lim

Ye Ji Lee

Jun Su Jeon

A semiconductor device includes an isolation structure having first and second sidewalls opposite each other, a first fin-shaped pattern in contact with the first sidewall and extending in the second direction, a second fin-shaped pattern in contact with the second sidewall and extending in the second direction, a first gate electrode on the first fin-shaped pattern, a first source/drain contact on the first and second fin-shaped patterns and extending between the first gate electrode and the element isolation structure, and a wiring structure on and connected to the first source/drain contact, wherein the first source/drain contact includes a lower contact intersecting the first and second fin-shaped patterns, an upper contact protruding from the lower contact, and a dummy contact, the wiring structure being in contact with the upper contact and not with the dummy contact.

Semiconductor device

A semiconductor device including a field insulating layer, which surrounds at least a part of side walls of each of first and second active patterns on a substrate, the field insulating layer including a protrusion protruding upwardly in a vertical direction between the first active pattern and second active pattern, respectively.

A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern.

A semiconductor device includes a first fin-shaped pattern which extends lengthwise in a first direction, a second fin-shaped pattern which is spaced apart from the first fin-shaped pattern in a second direction and extends lengthwise in the first direction, a first gate electrode extending lengthwise in the second direction on the first fin-shaped pattern, a second gate electrode extending lengthwise in the second direction on the second fin-shaped pattern, a first gate separation structure which separates the first gate electrode and the second gate electrode and is at the same vertical level as the first gate electrode and the second gate electrode, and a first source/drain contact extending lengthwise in the second direction on the first fin-shaped pattern and the second fin-shaped pattern. The first source/drain contact includes a first lower source/drain contact region which intersects the first fin-shaped pattern and the second fin-shaped pattern, and a first upper source/drain contact region which protrudes from the first lower source/drain contact region, and the first upper source/drain contact region does not overlap the first gate separation structure in the first direction.

A semiconductor device includes a substrate having a first power supply region, a second power supply region, and a cell region therein. The cell region extends between the first power supply region and the second power supply region. A first active region and a second active region are provided, which extend side-by-side within the cell region. A first power supply wiring is provided, which extends in the first direction within the first power supply region. A first source/drain contact is provided, which connects the first active region and the second active region. A second source/drain contact is provided, which connects the first active region and the first power supply wiring. The first source/drain contact includes a first recess portion disposed inside an intermediate region between the first active region and the second active region.

Semiconductor devices and methods for fabricating the same

A semiconductor device including a field insulating layer, a part of which protrudes upwardly in a vertical direction on an element isolation region between a first active region and a second active region may be provided.

A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Semiconductor device having fin-type active patterns with shared contact plugs

A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a gate electrode extending in a second direction intersecting the first direction on the active pattern, a gate spacer extending in the second direction along side walls of the gate electrode, an interlayer insulating layer contacting side walls of the gate spacer, a trench formed on the gate electrode in the interlayer insulating layer, a first capping pattern provided along side walls of the trench, at least one side wall of the first capping pattern having an inclined profile, and a second capping pattern provided on the first capping pattern in the trench.

A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.

Semiconductor device and method for fabricating the same

A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.

A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

A semiconductor device includes an active pattern extending in a first horizontal direction on a substrate, a gate electrode extending in a second horizontal direction across the active pattern, and including a first portion, and a second portion protruding upward from the first portion in a vertical direction, a capping pattern extending in the second horizontal direction on the gate electrode, and a gate contact disposed on the second portion of the gate electrode, overlapping the active pattern, and penetrating the capping pattern to connect the gate electrode.

Semiconductor device and method of fabricating same

A semiconductor device includes a substrate having an active region, a gate structure on the active region, the gate structure including a gate dielectric layer and a gate electrode layer, and the gate electrode layer having a rounded upper corner, and gate spacer layers on side surfaces of the gate structure, the gate spacer layers having an upper surface at a lower height level than an upper surface of the gate electrode layer.

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Hwaseong-si, South Korea

Deok Han Bae