Applied Materials, Inc.

Cavendish Kinetics Limited

Dennis J Yost

David Wingto Cheung

Gerald Z Yin

Wai-Fan Yau

Yunsang Kim

Farhad K Moghadam

Judy H Huang

Claes H Bjorkman

Kuowei Liu

Betty Tang

Hongquing Shan

Nasreen Gazala Chapra

Min Melissa Yu

Steven Verhaverbeke

Roman Gouk

Michael C Smayling

Robin W Cheung

Brian J Brown

James S Papanu

Han-Wen Chen

Jianshe Tang

Vikram Joshi

Joseph Damian Gordon Lacey

Thomas L Maguire

Ching-Hwa Weng

John H Madok

Melissa Min Yu

The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

CMP process flow for MEMS

Cleaning solutions and cleaning methods targeted to particular substrates and structures in semiconductor fabrication are described. A method of cleaning fragile structures having a dimension less than 0.15 um with a cleaning solution formed of a solvent having a surface tension less than water while applying acoustic energy to the substrate on which the structures are formed is described. Also, a method of cleaning copper with several different cleaning solutions, and in particular an aqueous sulfuric acid and HF cleaning solution, is described. Also, methods of cleaning both sides of a substrate at the same time with different cleaning solutions applied to the top and the bottom are described.

Cleaning submicron structures on a semiconductor wafer surface

According to one aspect of the present invention, a method and apparatus for cleaning a semiconductor substrate is provided. The method may include supporting a semiconductor substrate, the semiconductor substrate having a surface, and dispensing an amount of semiconductor substrate processing liquid onto the surface of the semiconductor substrate, the amount of semiconductor substrate processing liquid being such that substantially none of the semiconductor substrate processing liquid flows off the surface of the semiconductor substrate. The semiconductor substrate processing fluid may form a standing puddle on the surface of the semiconductor substrate. The semiconductor substrate may be rotated while the semiconductor substrate processing liquid is on the surface of the semiconductor substrate such that substantially all of the amount of semiconductor substrate processing liquid remains on the surface of the semiconductor substrate during said rotation.

Method and apparatus for cleaning semiconductor substrates

The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures. In one embodiment, spectral data collected from a given substrate is used to generate a current or voltage spectral signature. This spectral signature may then be compared to a reference spectral density signature to predict reliability of a feature structure of a substrate in processing and feedback to the substrate processing system for substrate processing control. Embodiments of the invention further include computer-readable media containing instructions for controlling the substrate processing system, and computer program products having computer-readable program code embodied therein for controlling the substrate processing system and inspecting defects on semiconductor features.

Early detection of metal wiring reliability using a noise spectrum

A method and apparatus for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufacturing facility where the design release is used for producing the layout of the integrated circuit and the design intent information is coupled to the equipment, especially the metrology equipment, within the IC manufacturing facility. As such, the design intent information can be used to optimize processing during IC fabrication to achieve optimization of the critical characteristics intended by the designer.

Method and apparatus for capturing and using design intent in an integrated circuit fabrication process

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Integrated low k dielectrics and etch stops

Integrated low K dielectrics and etch stops

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Los Gatos, CA, United States of America

Dennis J Yost