Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk Corporation

University of California

Dengtao Zhao

Deepanshu Dutta

Nima Mokhlesi

Xiang Yang

Henry Chin

Yongke Sun

Kroum Stanimirov Stoev

Haibo Li

Huai-Yuan Tseng

Peng Zhang

Jui-Yao Yang

Guirong Liang

Zhiping Zhang

Jiahui Yuan

Ravi J Kumar

Tapan Samaddar

Mei-Man L Syu

Abhijith Prakash

Jiacen Guo

Muhammad Masuduzzaman

Yi Song

Nan Lu

Masaaki Higashitani

Yanli Zhang

Gerrit Jan Hemink

Ken Oowada

Anubhav Khandelwal

Sarath Chandran Puthenthermadam

Wei Cao

Chin-Yi Chen

Deepak Chandra Sekar

Zhenming Zhou

Peter Rabkin

Man Lung Mui

Jayavel Pachamuthu

Yu-Chung Lien

Seungpil Lee

Wei Zhao

Hao Nguyen

Zhongguang Xu

Guangming Lu

Jin Liu

Shinji Sato

Xue Bai Pitner

Matthias Baenninger

Ruigang Li

Sanghyun Lee

Bei Li

Jianlin Liu

Heguang Li

Kun-Huan Shih

Yan Zhu

Ryohei Shoji

Weiyi Li

A block of non-volatile memory cells is divided into a first sub-block and a second sub-block. Programming non-volatile memory cells of the second sub-block after programming non-volatile memory cells of the first sub-block comprises boosting unselected channels in the second sub-block to a boosted condition; prior to boosting unselected channels in the second sub-block to the boosted condition, boosting unselected channels in the first sub-block to the boosted condition to pre-charge the channels of the second sub-block; and applying a program voltage to a selected word line of the second sub-block while channels in the first sub-block are in the boosted condition and channels in the first sub-block are in the boosted condition.

Non-volatile memory with efficient precharge in sub-block mode

Memory cells of a second sub-block are programmed by pre-charging channels of unselected memory cells connected to the selected word line, boosting the pre-charged channels of unselected memory cells and applying a program voltage to selected non-volatile memory cells connected to the selected word line. The pre-charging includes applying one or more overdrive voltages to word lines connected to memory cells of a first sub-block to provide a conductive path from memory cells of the second sub-block through the first sub-block to a source line and maintaining the word lines connected to memory cells of the first sub-block at one or more overdrive voltages while ramping down signals at the end of the pre-charging. Dummy word lines, positioned between sub-blocks, are maintained at a resting voltage during the boosting in order to cut-off channels of memory cells in the second sub-block from channels of memory cells in the first sub-block.

Non-volatile memory with dummy word line assisted pre-charge

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.

Asymmetric VREADK to reduce neighboring word line interference in a memory device

A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

Dual-way sensing scheme for better neighboring word-line interference

A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines, where the plurality of word lines are grouped into a plurality of zones based on a size of a word line switch transistor associated with each word line of the plurality of word lines. The memory device also includes a bitline biasing circuit for providing a negative biasing voltage to a bitline corresponding to a memory cell of the selected word line during programming of the selected word line and the bitline biasing circuit is configured to set a magnitude of the negative biasing voltage based on which zone of the plurality of zones the selected word line is in.

Enabling significant scaling of wordline switch with wordline dependent negative bitline voltage

A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

Erase method for non-volatile memory with multiple tiers

Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells. At the end of the pre-charging, the dummy word lines are ramped down to a resting voltage prior to lowering the data word lines to one or more resting voltages.

Non-volatile memory with early dummy word line ramp down after precharge

A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

Non-volatile memory with differential temperature compensation for super page programming

Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.

Non-volatile memory with tier-wise ramp down after program-verify

A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.

Memory device that is optimized for operation at different temperatures

Non-volatile memory with differential temperature compensation for bulk programming

A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.

Non-volatile memory with updating of read compare voltages based on measured current

To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

Non-volatile memory with sub-block based self-boosting scheme

Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

Reliability compensation for uneven NAND block degradation

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.

Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention

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Santa Clara, CA, United States of America

Dengtao Zhao