Freescale Semiconductor,inc.

Nxp USA, Inc.

Dehong Ye

Zhiwei Gong

Wei Gao

Zhijie Wang

Huchang Zhang

Jinzhong Yao

Zhigang Bai

Meiquan Huang

Jinsheng Wang

Hejin Liu

Zhe Li

Jiyong Niu

Chao Wang

Yanting Tian

Qing Chun He

Nageswara Rao Bonda

Wenjian Xu

A method of fabricating a 3D fan-out structure for an integrated circuit device includes providing a substrate carrier having first and second opposing surfaces and an aperture extending between the first and second surfaces. A first semiconductor die is bonded to the first surface of the substrate carrier such that the first die covers the aperture of the substrate carrier. An encapsulant and a second die are deposited within the aperture of the substrate carrier such that an active surface of the second die is exposed and coplanar with the second surface of the substrate carrier. One or more redistribution layers are then applied on the second surface of the substrate carrier to form a 3D fan-out structure.

Method of fabricating 3-dimensional fan-out structure

A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.

Die edge seal employing low-K dielectric material

An integrated circuit package has an exposed die pad with a trench and openings in the trench that are filled with encapsulant to form an encapsulant ring near the edges of the die pad. During assembly, the encapsulant passes through the openings and fills the trench to form the encapsulant ring. The ring helps to keep the die pad from separating from the encapsulant caused by thermal cycling. Air vents might be included in the die pad surface to allow air to escape from the trenches and the openings as they fill with encapsulant. Trenches from the openings to the die pad edge on the chip-side of the die pad might be included to increase adhesion of the encapsulant to the die pad.

Exposed pad integrated circuit package with mold lock

A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element.

Semiconductor devices and methods of assembling same

A method and apparatus are described for fabricating a low-pin-count chip package () including a die pad () for receiving an integrated circuit device and a plurality of connection leads () having recessed lead ends () at the outer peripheral region of each contact lead. After forming the package body () over the integrated circuit device, unplated portions () of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends () at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated () to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

Packaging process to create wettable lead flank during board assembly

A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is left exposed by the package body and provides a heat sink.

Dual die semiconductor package

A lead frame having a coating of organic compounds on its lead fingers prevents tin and flux from contaminating the lead fingers after die attach. The coating is removed prior to wire bonding. The coating allows for reliable second bonds (bond between wires and lead fingers) to be formed, decreasing the likelihood of non-stick and improving wire peel strength.

Growing community of inventors

Tianjin, China

Dehong Ye