International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Deepika Priyadarshini

Son Van Nguyen

Hosadurga K Shobha

Takeshi Nogami

Alfred Grill

Daniel C Edelstein

Donald Francis Canaperi

Christopher J Penny

Elbert Emin Huang

Lawrence Alfred Clevenger

Griselda Bonilla

Matthew T Shoudy

Sanjay C Mehta

Fee Li Lie

Stephen McConnell Gates

Gauri V Karve

Indira P Seshadri

Nicole A Saulnier

Spyridon Skordas

Leigh Anne H Clevenger

Thomas J Haigh, Jr

Tuan Anh Vo

Mona Abdulkhaleg Ebrish

Michael Rizzolo

Benjamin David Briggs

Vamsi Krishna Paruchuri

Wei Lin

Chao-Kun Hu

Kevin R Winstel

Dimitri R Kioussis

Douglas C La Tulipe, Jr

Isabel Cristina Chu

Seth L Knupp

Anthony K Stamper

Edmund Juris Sprogis

Joe Lee

Richard Francis Indyk

Brown Cornelius Peethala

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Method of forming copper interconnect structure with manganese barrier layer

Copper interconnect structure with manganese barrier layer

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

Microwave plasma and ultraviolet assisted deposition apparatus and method for material deposition using the same

A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

Structure and method for equal substrate to channel height between N and P fin-FETs

Interconnect structure

Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.

Low-temperature diffusion doping of copper interconnects independent of seed layer composition

Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.

Air gap and air spacer pinch off

Copper interconnect structure with manganese oxide barrier layer

A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a process temperature. The method may further include introducing precursors that include at least one dielectric providing gas species for a deposited layer and at least one hydrogen precursor gas into the process chamber of the deposition tool. The hydrogen precursor gas is introduced to the deposition chamber at a flow rate ranging from 50 sccm to 5000 sccm. The molar ratio for Hydrogen/Silicon gas precursor can be equal or greater than 0.05.

Robust high performance low hydrogen silicon carbon nitride (SiCNH) dielectrics for nano electronic devices

Growing community of inventors

Guilderland, NY, United States of America

Deepika Priyadarshini