Cadence Design Systems, Inc.

Deepak Soi

Alessandra Nardi

Antonino Armato

Francesco Lertora

Sourav Nandy

Shachindra Sharma

Devices, methods, non-transitory computer readable media, and other embodiments are described for automatic gate-level functional safety (FS) analysis and associated circuit design operations. One embodiment involves accessing register transfer level (RTL) design data, and accessing a set of FS data associated with an initial circuit design describing one or more failure modes associated with a plurality of circuit elements, an associated FS design criterion for each failure mode of the one or more failure modes, and one or more associations between the plurality of circuit elements and the one or more failure modes. The embodiment then involves generating a gate-level netlist using the RTL design data, mapping the one or more associations between the plurality of circuit elements from the RTL design data and the one or more failure modes to the gate-level netlist, and generating an updated set of FS data using the mapping of the one or more associations to the gate-level netlist.

Automatic gate-level FS analysis and FMEDA

Method, apparatus, and computer readable medium for restructuring a software program hierarchy having interface files and implementation files that include the interface files are described. In one example, dependencies between program units in the interface files and the implementation files are determined. The dependencies are represented as a plurality of bit strings. Correlated bitstrings of the plurality of bit strings are clustered into a plurality of partitions. Each of the plurality of partitions is transformed into corresponding program units. New interface files are respectively created having the corresponding program units for each of the plurality of partitions.

Growing community of inventors

Fremont, CA, United States of America

Deepak Soi