Intel Corporation

Deepak S Rao

Charles Henry Wallace

Mohit K Haran

Paul Anton Nyhus

Ruth Amy Brain

Jason W Klaus

Reken Patel

James Jeong

Robert M Bigwood

Marvin Young Paik

Debashish Basu

Alexander F Kaplan

Seungdo An

Daniel James Bahr

Kilhyun Bang

An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

Via contact patterning method to increase edge placement error margin

Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures

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Portland, OR, United States of America

Deepak S Rao