Intel Corporation

Deepak Rameshkumar Tanna

Michael T Klinglesmith

Terrence Huat Hin Tan

Rehan M Sheikh

Shi Hou Chong

Kok Hin Oon

Sukhbinder Takhar

Wai Loon Yip

Yudhishthira Kundu

In one embodiment, an apparatus includes: a port circuit to receive a configuration write from a source circuit; a save restore memory coupled to the port circuit to store information of a plurality of control and status registers (CSRs); and a configuration network coupled to the port circuit, the configuration network coupled to a plurality of nodes, each of the plurality of nodes comprising at least one CSR. The port circuit may be configured to send the configuration write to a first node of the plurality of nodes and to the save restore memory. Other embodiments are described and claimed.

Saving and restoring configuration and status information with reduced latency

Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.

Die stack override for die testing

Growing community of inventors

Bengaluru, India

Deepak Rameshkumar Tanna