Fairchild Semiconductor Corporation

Semiconductor Components Industries, LLC

Moxtek, Inc.

Motex, Inc.

Dean E Probst

Steven Paul Sapp

Joseph Andrew Yedinak

Daniel S Calafut

Robert Herrick

Bruce Douglas Marchant

Duc Q Chau

Becky Losee

Christopher Boguslaw Kocon

Ashok Challa

Izak Bencuya

Hamza Yilmaz

Prasad Venkatraman

Thomas E Grebs

Gary M Dolny

Brian Sze-Ki Mo

Peter Austin Burke

Nathan Lawrence Kraft

Rodney S Ridley

Daniel Marvin Kinzer

Bin Wang

Zia Hossain

Balaji Padmanabhan

Mark Alan Davis

James J Murphy

Paul Thorup

Shengling Deng

Jeffery Allen Neuls

Gary Horst Loechelt

Eric W Gardner

Austin L Huang

Alan Elbanhawy

Peter H Wilson

Michael D Gruenhagen

Hua Li

Fred Session

Ted Wangensteen

Gordon K Madson

Muh-Ling Ger

Brian S Mo

Qihong Wu

Mark L Rinehimer

Peter McGrath

Suku Kim

Babak S Sani

Tirthajyoti Sarkar

Rumyana Petrova

Dixie Dunn

John L Benjamin

Masaichi Eda

Takashi Hiroshima

Toshimitsu Taniguchi

Mitsuru Soma

Hui Chen

Richard Stokes

Mike Black

Steven Marks

Debra S Woolsey

Jeffrey P Gambino

Densen B Cao

Takashi Ogura

James N Pan

David T Price

Christopher Lawrence Rexer

Bigildis Dosdos

Hossein Paravi

Jason Higgs

Scott L Hunt

Donald Roy

Santosh Menon

Jayson Preece

In a general aspect, a method can include forming well region of one conductivity type in a semiconductor region of another conductivity type An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The method can further include forming at least one dielectric region in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

Reverse recovery charge reduction in semiconductor devices

In some aspects, the techniques described herein relate to a circuit including: a metal-oxide semiconductor field-effect transistor (MOSFET) including a gate, a source, and a drain; and a snubber circuit coupled between the drain and the source, the snubber circuit including: a diode having a cathode and an anode, the cathode being coupled with the drain; a capacitor having a first terminal coupled with the anode, and a second terminal coupled with the source; and a resistor having a first terminal coupled with the anode and the first terminal of the capacitor, and a second terminal coupled with the source.

Integrated transistor and resistor-diode-capacitor snubber

In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

In one embodiment, a semiconductor device is formed having a plurality of active trenches formed within an active region of the semiconductor device. A first insulator is formed along at least a portion of sidewalls of each active trench. A perimeter termination trench is formed that surrounds the active region. The perimeter termination trench is formed having a first sidewall that is adjacent the active region and a second sidewall that is opposite the first sidewall. An insulator is formed along the second sidewall that has a thickness is greater than an insulator that is formed along the first sidewall.

Semiconductor device and structure therefor

A circuit and physical structure can help to counteract non-linear Cassociated with power transistors that operate at higher switching speeds and lower R. In an embodiment, a component with a pn junction can be coupled to an n-channel IGFET. The component can include a p-channel IGFET, a pnp bipolar transistor, or both. A gate/capacitor electrode can be within a trench that is adjacent to the active regions of the component and n-channel IGFET, where the active regions can be within a semiconductor pillar. The combination of a conductive member and the semiconductor pillar of the component can be a charge storage component. The physical structure may include a compensation region, a barrier doped region, or both. In a particular embodiment, doped surface regions can be coupled to a buried conductive region without the use of a topside interconnect or a deep collector type of structure.

Electronic device including a charge storage component

An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

Electronic device including doped regions and a trench between the doped regions

A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each first type of device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. Each second type of device cell in the gate or shield contact area includes a trench that is wider and deeper than the trench in the first type device cell.

Trench MOSFET contacts

Method of forming a semiconductor device and structure therefor

A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

Stacked transistor assembly with dual middle mounting clips

In one embodiment, a method of forming a semiconductor device forms gate trenches in a semiconductor substrate. A portion of the material between the trenches is narrowed and another material is formed on sidewalls of the narrowed portion that is substantially not etched by an etchant that etches the material of the portion of the material between the trenches. Source and gate contact openings are formed together.

Method of forming a semiconductor device

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Trench-based power semiconductor devices with increased breakdown voltage characteristics

A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. The second type of device cell includes a trench that is wider than the trench in the first device cell, but a mesa of the second type of device cell has about the same width as the mesa of the first type of device cell. Having about the same width, the mesa in the second type of device cell in the contact area has similar breakdown characteristics as a mesa in the first type of device cell in the active area of the device.

In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.

Transistor device having a pillar structure

Cube polarizers can be designed for substantially equal optical path lengths of a reflected beam and a transmitted beam. For example, dof FIG.can define a distance between a plane (face plane) of the outer face (outer face) of a second prismand the first edge (first edge) of the first prism, and dcan be less than 400 micrometers. As another example, an optical path length differential between a transmitted beam and a reflected beam (|OPL&#x2212;OPL|) can be where t is a thickness of the substrate between the first surface and the second surface of the substrate and nis an index of refraction of the first prism.

Cube polarizer

Growing community of inventors

West Jordan, UT, United States of America

Dean E Probst