Taiwan Semiconductor Manufacturing Comp. Ltd.

De-Fang Chen

Huan-Just Lin

Chun-Hung Lee

Teng-Chun Tsai

Li-Ting Wang

Cheng-Tung Lin

Chao-Cheng Chen

Ming-Ching Chang

Chih-Tang Peng

Ching-Feng Fu

Chien-Hsun Wang

Yih-Ann Lin

Chia-Ying Lee

Hui-Cheng Chang

Yu-Chan Yen

Tzu-Yen Hsieh

Yung-Cheng Lu

Chun-Kuang Chen

Chi-Cheng Hung

Wei-Liang Lin

Bing-Hung Chen

Huang-Yi Huang

Ming-Hsing Tsai

Yu-Tien Shen

Tze-Liang Lee

Wei-Yang Lee

Tai-Chun Huang

Hung-Ta Lin

Ru-Gun Liu

Tsai-Sheng Gau

Chin-Yuan Tseng

Wei-Jen Lai

Bi-Ming Yen

Chun-Liang Tai

Kuo-Pi Tseng

Chang Ming-Ching

Ting-Wen Shih

Ryan Chia-Jen Chen

Chien-Hao Chen

Yu Chao Lin

Chia-Wei Chang

Ting-Yeh Chen

Chan Syun David Yang

Po-Cheng Wang

Weng Cheng

A semiconductor structure includes semiconductor layers vertically stacked above a substrate, a gate structure wrapping around each of the semiconductor layers, a gate spacer disposed on sidewalls of the gate structure, a source/drain (S/D) feature abutting the semiconductor layers, and an S/D contact landing on a top surface of the S/D feature. In a cross-sectional view along a lengthwise direction of the semiconductor layers, a topmost point of the top surface of the S/D feature is above a top surface of a topmost one of the semiconductor layers, and a bottommost point of the top surface of the S/D feature is below the top surface of the topmost one of the semiconductor layers.

Semiconductor devices with modified source/drain feature and methods thereof

According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Vertical device having a protrusion source

A device includes a substrate, a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a bottom dielectric structure. The channel layer is over the substrate. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer and are connected to the channel layer. The bottom dielectric structure is between the first source/drain epitaxial structure and the substrate. A maximum width of the first source/drain epitaxial structure is greater than or equal to a maximum width of the bottom dielectric structure in a cross-sectional view.

Semiconductor device and manufacturing method thereof

A method includes providing a semiconductor structure including a fin protruding from a substrate, where the fin includes first semiconductor layers and second semiconductor layers, recessing the fin to form a source/drain (S/D) recess, forming an S/D feature in the S/D recess, trimming the S/D feature, depositing a dielectric layer to cover the S/D feature, forming a contact hole in the dielectric layer to expose the S/D feature, and forming a metal contact in the contact hole.

A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Method of forming an integrated circuit using a patterned mask layer

Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Method for improved critical dimension uniformity in a semiconductor device fabrication process

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.

Structure and formation method of semiconductor device with nanosheet structure

A device includes a substrate, a channel layer, a gate structure, a source/drain epitaxial structure, and a bottom dielectric structure. The channel layer is over the substrate. The gate structure is over the substrate and surrounds the channel layer. The source/drain epitaxial structure is over the substrate and is connected to the channel layer. The bottom dielectric structure is between the source/drain epitaxial structure and the substrate.

According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Method of forming isolation layer

A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.

Semiconductor device with multiple threshold voltage and method of fabricating the same

A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Self-aligned nanowire formation using double patterning

Vertical device having a protrusion structure

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Hsinchu, Taiwan

De-Fang Chen