Lsi Logic Corporation

Dawn M Lee

Ronald J Nagahara

Jayanthi Pallinti

Ron J Nagahara

Richard S Osugi

Nicholas F Pasch

Weidan Li

Ming-Yi Lee

Shumay X Dou

Colin D Yates

Marilyn Hwan

A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure. The mask is then removed and the structure is subject to a chemical mechanical polishing step to planarize the upper surface of the structure. The prior removal of a portion of the overall volume of the one or more dielectric layers in the region overlying the raised portions of the integrated circuit structure before the planarization step results in a shortening of the CMP process which, in turn, results in a shortening of the time during which the structure is subject to the mechanical stresses of the CMP process. This inhibits or eliminates cracking of the low k dielectric layer adjacent the region of the low k dielectric layer over raised portions of the underlying integrated circuit structure.

Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures

A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform. The planarization process include: removing portions of the filler layer over the liner layer on the upper surface of the substrate until portions of the underlying liner layer on the upper surface of the substrate are exposed; treating the exposed portions of the liner layer to inhibit removal of the exposed liner layer portions; continuing to remove the remainder of the filler layer on the liner layer over the upper surface of the substrate until all of the underlying liner layer on the upper surface of the substrate is exposed; and then removing the liner layer over the upper surface of the substrate and over the filler layer in the trenches until all of the liner layer is removed from the upper surface of the substrate; whereby removal of all of the filler layer on the liner layer over the upper surface of the substrate, while inhibiting removal of the liner layer over the upper surface of the substrate until such filler layer removal on the liner layer over the upper surface of the substrate is completed, will result in formation of a planarized surface on the upper surface of the substrate, and the upper surfaces of the filler layer and the liner layer in the trenches.

Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate

Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished. In one embodiment, the second mechanism is arranged to apply both positive pressure and negative pressure substantially simultaneously across the second surface of the semiconductor wafer.

Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing

A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer. Trenches and/or vias are formed through the ARC layer and the oxide dielectric layer. These trenches and/or vias are then filled by depositing at least one metal layer over the ARC layer. Excess trench and/or via filler metal is then removed from the top surface of the ARC layer by subjecting the metal to a CMP step which is selective to the ARC layer, thereby permitting the ARC layer to function as a CMP stop layer which protects the underlying oxide dielectric layer from exposure to the CMP process. Since the ARC layer has a lower etch rate, in the CMP process to remove metal, than does the oxide dielectric layer, the formation of dished or concave regions in the surface is inhibited, including those regions where the trenches and/or vias are closely spaced apart.

Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure

A polishing pad for chemical-mechanical polishing of an integrated circuit surface is described. The polishing pad includes a first polishing area having a first value of a physical property; and a second polishing area having a second value of said physical property, which said second value is different from the first value, such that during chemical-mechanical polishing of an integrated circuit surface, the integrated circuit rotates and oscillates on the polishing pad so that a substantial portion of the integrated circuit surface contacts both the first and second polishing areas, wherein a width of said first and second polishing areas is greater than about 40 mils.

Polishing pad surface for improved process control

An end effector to facilitate conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface is described. The end effector includes an inwardly recessing contact surface capable of attaching to a conditioning disk having a conditioning surface such that the conditioning surface conforms to a substantial portion of the polishing pad, which protrudes outwardly under operation and thereby effectively conditions a substantial portion of the polishing pad. The present invention also describes a conditioning disk for effectively conditioning a surface of a polishing pad used in chemical-mechanical polishing of a substrate surface. The conditioning disk includes (i) a second surface capable of attaching to a contact surface of an end effector and (ii) an inwardly recessing conditioning surface that conforms to a substantial portion of said polishing pad, which protrudes outwardly under operation, and thereby effectively conditions the polishing pad. Processes and a chemical-mechanical polishing apparatuses employing the inventive end effectors or conditioning disks are also described.

Effective pad conditioning

A substrate holder assembly for forming a substantially uniformly polished substrate surface during chemical-mechanical polishing is described. The substrate holder assembly includes a carrier film having: (A) a porous layer with (i) a first surface with an outwardly protruding dome shaped region that applies pressure on at least a portion of the substrate surface during chemical-mechanical polishing and a location of the protruding dome shape is aligned with a location of an area of substrate surface that is likely to be underpolished, (ii) a second surface facing a contact surface of a backing plate; and (B) a pressure sensitive adhesive backing layer for affixing the carrier film to the contact surface of the backing plate under sufficient pressure.

Modified carrier films to produce more uniformly polished substrate

A process for compensating for degradation of a first polishing pad during polishing on the first polishing pad of a plurality of substrate surfaces that have substantially similar film stacks is described. The process includes: (a) characterizing a test polishing pad, which characterization includes determining changes in film removal rates of layers of the film stack during polishing of the plurality of the substrate surfaces on the test polishing pad; (b) polishing a first substrate surface on the first polishing pad, which is substantially similar to the test polishing pad, under a first set of polishing conditions; and (c) polishing a second substrate surface on the first polishing pad under a second set of polishing conditions. A difference between the second set of polishing conditions and the first set of polishing conditions is designed to minimize the changes in the film removal rates of the layers of the film stack and thereby compensate for degradation of the first polishing pad.

In-situ chemical-mechanical polishing slurry formulation for

An apparatus is provided for conditioning a polishing pad used for chemical-mechanical polishing. The apparatus comprises the retainer ring used to retain the semiconductor wafer against the polishing pad. Accordingly, the retainer ring serves a dual purpose: to retain the wafer in proper CMP position as well as condition the polishing surface while polishing of the wafer. The retainer ring includes an inner surface defining an opening to receive the semiconductor wafer. Dimensioned radially outside the inner surface is an outer surface. Placed on the distal ends between the inner and outer surfaces is an abrasive surface. The abrasive surface extends along a plane parallel to the retained frontside surface of the wafer. Both the wafer and the abrasive surface contact the polishing surface either in a rotation about a stationary axis or orbital movement about that axis. The wafer surface can be pressed to a greater or lesser extent against the polishing pad independent of the pressure exerted by the abrasive surface on that pad radially outside the wafer.

Dual purpose retaining ring and polishing pad conditioner

A substrate holder assembly for retaining a substrate during chemical mechanical polishing is described. The substrate holder assembly includes: (i) a backing plate including a contact surface adapted for supporting components of the substrate holder assembly and the substrate; (ii) a shim positioned adjacent the contact surface of the backing plate for applying pressure on the substrate during chemical-mechanical polishing; and (iii) a carrier film disposed adjacent the shim such that at least a portion of the carrier film adjacent the shim protrudes outwardly.

Shimming substrate holder assemblies to produce more uniformly polished

A conveying assembly in a conditioning sub-assembly for conveying a conditioning surface to a polishing pad during conditioning is described. The conveying assembly includes an arm and a guiding component connected to the arm and adapted to guide the conditioning surface about the conveying assembly, thereby allowing another area of the conditioning surface to advance and become available for conditioning.

Use of abrasive tape conveying assemblies for conditioning polishing pads

An end effector to facilitate conditioning of a surface of a polishing pad used in chemical-mechanical polishing of an substrate surface is described. The end effector includes a rigid body including a contact surface capable of being attached to a conditioning disk and having a predetermined non-planar region that is adapted to at least one of (i) effectively maintain a non-planar area on the surface of the polishing pad and (ii) shape the polishing pad, when the end effector is employed to condition the polishing pad.

Shaping polishing pad to control material removal rate selectively

Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions to a polishing pad are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a surface of a semiconductor wafer includes a polishing pad with a first surface and a second surface. The first surface of the polishing pad is arranged to contact the surface of the semiconductor wafer in order to polish the surface of the semiconductor wafer. The apparatus also includes a mechanism which is used to apply a non-uniform pressure distribution over the second surface of the polishing pad, wherein applying the non-uniform pressure distribution to the polishing pad facilitates evenly polishing the surface of the semiconductor wafer. In one embodiment, the mechanism for applying the non-uniform pressure distribution to the polishing pad is an air bladder arrangement.

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Morgan Hill, CA, United States of America

Dawn M Lee