Altera Corporation

Intel Corporation

David Wolk Mendel

Bruce B Pedersen

Gregg William Baeckler

Richard G Cliff

Francis B Heile

Keith Duwel

Joseph Huang

Kerry S Veenstra

Chiakang Sung

Bonnie I Wang

Huy X Ngo

Jakob Raymond Jones

Sergey Yuryevich Shumarayev

Srinivas T Reddy

Jeffrey Erik Schulz

Michael David Hutton

Christopher F Lane

James G Schleicher

Vaughn Betz

Victor Maruri

Peter J Kazarian

Rakesh H Patel

Wei-Jen Huang

Tony K Ngai

Dinesh D Patil

Gary Brian Wallichs

Fung Fung Lee

Jim Park

Andrew Leaver

Cameron R McClintock

Sinan Kaptanoglu

David Edward Jefferson

L Todd Cope

Craig S Lytle

Rina Raman

Herman Henry Schmit

Dana How

Ninh D Ngo

Lu Zhou

Han Hua Leong

Gary Lai

Marwan A Khalaf

Mahesh A Iyer

Ramanand Venkata

Stephen D Brown

Curt Wortman

Babette Van Antwerpen

Terry Borer

Alan Louis Herrmann

Richard Yuan

Carl Ebeling

Mike Hutton

Kevin Chan

Rajiv Dattatraya Kane

Brent Alan Fairbanks

John Tse

Ian Chesal

Robert R Bielby

Robert Richard Noel Bielby

Boris Ratchev

Yaska Sankar

Tim Tri Hoang

Weiqi Ding

Chandra Mohan Jha

Jinyong Yuan

Divya Vijayaraghavan

Ning Xue

Henry Y Lui

Nicholas Neal

Jie Shen

Kumara Tharmalingam

Kelly P Lofgreen

Michael Menghui Zheng

Andy Turudic

Triet M Nguyen

Renxin Xia

Andrew J Bellis

Allan Thomas Davidson

Neville Carvalho

Bruce B Pederson

Khong Seng Foo

Haiyun Yang

Sita Rama Chandrasekhar Mallela

Yean-Yow Hwang

Nigel Antoine Gulstone

Joel Martinez

Kalyan Kankipati

Frederic Richard

Ru Yin Ng

Geok Sun Chong

Greg William Baeckler

Seungmyon Park

Bruce B Pendersen

Dong-Myung Choi

A data transmission system includes a transmitter circuit. The transmitter circuit receives regular data bits and auxiliary data bits. The transmitter circuit encodes a first subset of the regular data bits to generate a first subset of encoded data comprising pairs of symbols that are used in quadrature amplitude modulation. The transmitter circuit encodes the auxiliary data bits and a second subset of the regular data bits to generate a second subset of the encoded data comprising at least one pair of symbols that are unused for encoding by the quadrature amplitude modulation. The transmitter circuit generates a modulated output signal that indicates the first and second subsets of the encoded data using pulse amplitude modulation.

Systems and methods for transmitting and receiving auxiliary data

A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

Seemingly monolithic interface between separate integrated circuit die

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Interface bridge between integrated circuit die

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

Multichip package with protocol-configurable data paths

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1&#xd7; mode or 2&#xd7; mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

Particular embodiments described herein provide for an electronic device that can be configured to determine that a packet needs a timestamp, determine an initial timestamp for a reference block, communicate the reference block to a monitor engine, receive an asynchronous pulse from the monitor engine after the monitor engine received the reference block, determine a synchronization timestamp for the asynchronous pulse, and determine the timestamp for the packet based on the initial timestamp for the reference block and the synchronization timestamp for the asynchronous pulse.

Generating a timestamp

The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

Universal transceiver container

The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing margins such that operating the circuit design implementation with the integrated circuit meets timing constraints. The voltage identification controller may direct a voltage regulator, which may be included in the integrated circuit or located outside the integrated circuit, to reduce the supply voltage level from the nominal supply voltage level to the reduced voltage level, thereby reducing the power consumption of the integrated circuit.

Methods and apparatus for regulating the supply voltage of an integrated circuit

An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

Techniques for signal skew compensation

Growing community of inventors

Sunnyvale, CA, United States of America

David Wolk Mendel