International Business Machines Corporation

Infineon Technologies North America Corp.

Infineon Technologies Ag

Globalfoundries Inc.

David William Abraham

Philip Louis Trouilloud

John Michael Cotte

Daniel Christopher Worledge

Jay Michael Gambetta

Jerry M Chow

Antonio D Corcoles Gonzalez

Mary Beth Rothwell

James Robert Rozen

Hemantha Kumar Wickramasinghe

Timothy Joseph Chainer

Michael C Gaidis

Sivananda K Kanakasabapathy

William Joseph Gallagher

George Andrew Keefe

Joerg Dietrich Schmid

Eugene John O'Sullivan

Matthias Steffen

Anthony Paul Praino

Mark E Re

John Aaron Smolin

John Casimir Slonczewski

Roger Hilsen Koch

Shouheng Sun

Stuart P Parkin

Snorri Thorgeir Ingvarsson

Josephine B Chang

Ying Di Zhang

Christian Lavoie

Gordon James Smith

Alejandro Gabriel Schrott

Hal Hjalmar Ottesen

Anthony J Annunziata

Solomon Assefa

Shawn Anthony Hall

Eric Peter Lewandowski

Janusz Jozef Nowak

Robert Stephen Olyha, Jr

Stephen L Brown

Oliver Dial

John De Brosse

Nicholas A Masluk

Karl-Friedrich Etzold

Philip Edward Batson

Niladri N Mojumder

Chanro Park

Erhard Theodor Schreck

Kevin Shawn Petrarca

Robert J Von Gutfeld

Eric Andrew Joseph

John Kenneth DeBrosse

Guohan Hu

Matthew Warren Copel

Wolfgang Raberg

Ferdinand Hendriks

Jonathan Zanhong Sun

Nicholas C M Fuller

Kenneth Gilbert Roessler

Roger W Cheek

Stuart S P Parkin

Francois Pagette

John Patrick Hummel

Yu Lu

Arunava Gupta

Steven Erik Steen

Joseph S Logan

Martin Patrick O'Boyle

James Michael Hammond

James Anthony Misewich

Timothy Phung

Richard Allen John

Muir Kumph

Danny C Wong

William M Holber

Martin A Klos

Robert M Stowell

Assefa Solomon

Ulrich Klostermann

Phillip L Trouilloud

A cryogenic electronics device includes a semiconductor chip. A substrate is flip-chip bonded to the semiconductor chip. A plurality of bump bonds are concentrated in a bump region of the semiconductor chip. A plurality of circuit elements are arranged in a predefined region of the semiconductor chip. The predefined region and the bump region are separate regions.

Electrical connections between dissimilar materials at cryogenic temperatures

A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.

Edge capacitive coupling for quantum chips

An electronic structure includes a first substrate having a first under bump metallization (UBM) region and a second UBM region formed thereon. One or more solder bumps is deposited onto the first UBM region. A downstop formed on the second UBM region is wider, shallower and more rigid than any one of the solder bumps formed on the first UBM region. A second substrate is joined to the first substrate by the one or more solder bumps located on the first UBM region, and a height of the downstop limits a distance between at least one of the first substrate and the second substrate, or between an object and at least one of the first substrate and the second substrate.

Downstop and bump bonds formation on substrates

A semiconductor device comprises a first chip layer, having a first chip layer front-side and a first chip layer back-side, a qubit chip layer, having a qubit chip layer front-side and a qubit chip layer back-side, the qubit chip layer front-side operatively coupled to the first chip layer front-side with a set of bump-bonds, a set of through-silicon vias (TSVs) connected to at least one of: the first chip layer back-side or the qubit chip layer back-side and a cap wafer metal bonded to at least one of: the qubit chip layer back-side or the first chip layer back-side.

Create a protected layer for interconnects and devices in a packaged quantum structure

Techniques regarding qubit chip assemblies are provided. For example, one or more embodiments described herein can include an apparatus that can comprise a qubit chip positioned on an interposer chip. The apparatus can also comprise an electrical connector in direct contact with the interposer chip. The electrical connector can establish an electrical communication between a wire and a contact pad of the interposer chip that is coupled to the qubit chip.

Interposer chips and enclosures for quantum circuits

A method for forming an electronic chip assembly. A first metal plate is coupled to a first side of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend at least to the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate, having a second cavity, is disposed to a second side of the substrate, and over the first cavity such that the electronic component is encased within the first and second cavities by the first and second metal plates.

Combined backing plate and housing for use in bump bonded chip assembly

Techniques for creating an offset embedded ground plane cutout for a qubit device to facilitate frequency tuning of the qubit device are presented. A qubit device can comprise a first substrate and second substrate in a flip-chip assembly. The qubit chip assembly can comprise a qubit component fabricated on the first substrate. The qubit component can comprise a Josephson junction (JJ) circuit that can be offset from a center point of the qubit component. The qubit chip assembly can comprise an embedded ground plane situated on a surface of the qubit chip assembly. A cutout section can be formed in the ground plane and positioned over the JJ circuit. The cutout section can enable access of an optical signal or magnetic flux to the JJ circuit. A frequency of the qubit component can be tuned based on application of the optical signal or magnetic flux to the JJ circuit.

Offset embedded ground plane cutout

A system for adjusting qubit frequency includes a qubit device having a Josephson junction and a shunt capacitor coupled to electrodes of the Josephson junction. A cantilevered conductor is separated from the shunt capacitor by a spacing. An adjustment mechanism is configured to deflect the cantilevered conductor to tune a qubit frequency for the qubit device.

Mechanically tunable superconducting qubit

A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

Semiconductor device including superconducting metal through-silicon-vias and method of making the same

A filter is provided and includes potting material formed into a body defining a through-hole. The body includes first and second opposing faces and a sidewall extending between the first and second opposing faces. The sidewall is formed to define first and second openings at opposite ends of the through-hole, first angles at an interface between the sidewall and the first face and second angles, which complement the first angles, at an interface between the sidewall and the second face.

Coaxial transmission line slot filter with absorptive matrix

A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.

Bump bonded cryogenic chip carrier

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

Multiple sized bump bonds

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Non-destructive testing of integrated circuit chips

Growing community of inventors

Ossining, NY, United States of America

David William Abraham