International Business Machines Corporation

David Stanasolovich

Ronald A Warren

Donna Rizzone Cote

William Alfred Syverson

Gangadhara Swami Mathad

Giorgio G Via

Murty S Polavarapu

Steven L Peterman

Charles P Breiten

Jeffrey R Barber

Jacob F Theisen

Harish N Kotecha

Hung Y Ng

Robert M Merkling, Jr

Madan M Nanda

Marc Jay Weiss

Lawrence Andrew Kropp

Dennis Sek-On Yee

Paul E Nixon

Susanna R Carbaugh

David D Meyer

A homogeneous marker is formed, possibly by the adsorption of trace amounts of an ambient material such as carbon monoxide gas, at a surface of a deposited material when the plasma in momentarily interrupted during plasma enhanced chemical vapor deposition or other deposition processes involving the presence of a plasma. When the deposited material is etched, the resulting crystal dislocations or adsorbed gas is detected as a marker by optical emission spectroscopy techniques. The accuracy of an end point determination of the etching process can be increased by providing a sequence of such markers within the bulk or volume of the deposited material. The markers, being merely an interface such as a slight crystal dislocation in otherwise homogeneous material, do not affect the electrical, chemical or optical properties of the remainder of the predetermined deposited material and thus the homogeneity of the deposited material is not significantly affected.

Precise endpoint detection for etching processes

Apparatus and method for cleaning/etching the surface of an article with sonic energy in the megahertz range which employ an anti-reflection mechanism within a recirculation tank. A tank having at least one side wall and a bottom structure holds a cleaning/etching liquid and a megasonic transducer is associated with the tank for projecting megasonic energy into the liquid. The anti-reflection mechanism is disposed within the tank in close association with the at least one sidewall or bottom structure of the tank to thereby minimize reflection of megasonic energy from the associated surface. Preferably, the megasonic transducer is associated with a first tank sidewall which opposes a second tank sidewall, and the anti-reflection mechanism is disposed adjacent the second tank sidewall. By way of example, the anti-reflection mechanism can comprise a stream of gas bubbles, a plurality of anechoic structures, or a combination of both gas bubbles and anechoic structures.

Apparatus for uniform cleaning of wafers using megasonic energy

Method for uniform cleaning of wafers using megasonic energy

A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

Self-aligned contact studs for semiconductor structures

A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygenplasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrroldone (NMP).

Process of forming a dual overhang collimated lift-off stencil with

Self-aligning process for fabricating a semiconductor structure and stud therefor on a semiconductor substrate comprises depositing a first material onto the substrate, depositing a second material onto the first material, removing excess portions of second material so as to form openings through the second material exposing excess portions of first material, whereby a selected portion of second material is retained and forms a sacrificial element, removing the excess portions of first material selectively to the substrate so as to extend the openings through the first material to the substrate, whereby a selected portion of first material is retained and forms the semiconductor structure, filling the openings with an insulating material, removing the sacrificial element selectively to the insulating material and the semiconductor structure for forming a contact window opening for allowing access to the semiconductor structure, and filling the contact window opening with stud material so as to contact the semiconductor structure for forming the stud.

Process for fabrication of a semiconductor structure and contact stud

A contact stud for semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

Process for fabricating self-aligned contact studs for semiconductor

A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygen plasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrrolidone (NMP).

Collimated metal deposition

A process for defining vias through a polyimide and silicon nitride layer is disclosed. After the deposition of a first layer of silicon nitride and a second layer of polyimide, a layer of photoresist capable of producing negatively sloped walls is then lithographically defined with a pattern of vias. After the photoresist is developed, the polyimide layer is etched with a CF.sub.4 O.sub.2 gas mixture using the developed photoresist layer as etch mask. The silicon nitride layer is then etched with a CF.sub.4 /H.sub.2 gas mixture using the etched polyimide layer as an etch mask.

Process for defining vias through silicon nitride and polyamide

A process for making borderless contacts through an insulating layer to active regions of a semiconductor device is disclosed. After deposition of a silicon nitride layer and an insulation glass layer on a substrate coating semiconductor devices, the contact windows are etched. The windows are etched through the glass layer with BCl.sub.2 or CHF.sub.3 /CF.sub.4 etch gases. Next, the windows are etched through the silicon nitride with CH.sub.3 F or O.sub.2 /CHF.sub.3 gases.

Method for making borderless contacts

A process for making metal contacts and interconnection lines which are self-aligned to each other is disclosed. After semiconductor devices are formed and an insulating/planarizing layer is deposited, a layer of polyimide is deposited. A pattern of trenches into which the metal interconnection lines will be deposited is formed in the polyimide layer. Next, a pattern of contacts to the underlying semiconductor devices is formed in a photoresist layer. This pattern of contacts is subsequently etched into the insulating/planarizing layer. Since both the patterned photoresist layer and the patterned polyimide layer are used as etch masks, the contact windows through the insulating/planarizing layer and the trenches in the polyimide layer will be aligned with respect to each other. After metal deposition, the metal contacts and interconnection lines will be self-aligned.

Process for making self-aligned contacts

A method of planarizing wide dielectric filled isolation trenches formed in the surface of a semiconductor surface is described. A self aligned mask is formed on the thick conformal layer of dielectric in the depressions over the wide trenches to protect the dielectric in those trenches from etching during planarization steps. The mask material is chosen to have etch characteristics different from the dielectric layer and a subsequent planarizing organic layer to allow selective etching of the mask material or dielectric without etching the other materials in the structure.

Planarization process for wide trench isolation

A method for providing increased dopant concentration in selected regions of semiconductors by providing field implant dopant in the transition region located below the 'bird's beak' region and between the field and active regions of a semiconductor. The method comprises the steps of: forming a thin insulating layer on the surface of a semiconductor substrate; depositing a thin anti-oxidant layer on the insulating layer; depositing a layer of photoresist on the anti-oxidant layer; selectively etching the anti-oxidant layer; ion-implanting the field region of the semiconductor substrate; providing spacers on the sides of the anti-oxidant layer; and oxidizing the semiconductor substrate.

Growing community of inventors

Montgomery, NY, United States of America

David Stanasolovich