Solid State Scientific Corporation

Sprague Electric Company

Allegro Microsystems, LLC

Ultratech Stepper, Inc.

David S Pan

Alexander H Owens

Mark A Halfacre

Wing K Huie

Brian K Rosier

Kanak C Sarma

David A Markle

Hwan J Jeong

Robert L Brown

Michael J Zunino

Richard B Ward

Mark S Wanta

A substrate alignment and exposure system is disclosed The alignment is performed by capturing an image of the substrate with a pattern recognition system, determining the offset from the alignment and moving the substrate relative to the reticle to be in alignment. A first optical alignment system which captures an image of a position of the substrate off of the primary axis of the exposure optics is used to perform pre-alignment. A second optical alignment system captures an image of the reticle and the substrate through the lens of the exposure optics. The pattern recognition system recognizes the alignment keys on the reticle, alignment targets on the substrate, and computes their positions and displacement from alignment. The relative alignment can be direct or inferred. Any angular and translational misalignment is calculated. The pattern recognition system then moves the substrate to be in alignment with the reticle. In the present invention, any arbitrary feature on the reticle and substrate, including device features or specialized alignment keys and targets used by other exposure systems, can be recognized by the pattern recognition system and used for alignment.

Pattern recognition alignment system

A method for making an integrated circuit includes forming patches of a silicon nitride mask over the areas where a high-current vertical DMOS and/or NPN transistor, where a vertical NPN transistor and where the NMOS and PMOS transistors of a CMOS pair are to be formed. The nitride mask also includes patches over a network of P-type isolation walls, and two special patches over two special areas at which N+ plugs for the DMOS and NPN transistors are to be formed. A heavy field oxide is grown everywhere except at the nitride patches. The two special patches are selectively removed and by heating and diffusing phosphorous from a POCl.sub.3 source from 950.degree. C. to 1100.degree. C. for at least 30 minutes, two very high conductivity N+ phosphorous plugs are formed through the epitaxial layer at a concentration of over 10.sup.20 phosphorous atoms/cm.sup.3, while the nitride serves to prevent the sensitive channel regions of the DMOS and CMOS transistors from phosphorous doping. This results in close self-alignment of the N+ plugs and their associated DMOS and NPN transistors leading to low on-resistance, to higher IC component density, to a high throughput rate at manufacturing and low cost.

Method of making integrated circuit with high current transistor and

A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.

Method for making a vertical power DMOS transistor with small signal

A memory device, based upon a field effect transistor having a floating gate is constructed for use in a silicon integrated circuit array of similar memory devices. The memory device includes only two polysilicon layers, a portion of each polysilicon layer being connected to each other through a via hole in an intervening silicon dioxide layer to form the floating gate.

Memory device with interconnected polysilicon layers and method for

A CMOS EPROM is made wherein the typical EPROM device is an N-channel IGFET having a control gate self-aligned with an underlying floating gate. In this process the EPROM floating gate and the gates of both the P-channel and N-channel peripheral circuit transistors are formed from a first deposited polysilicon layer. The EPROM control gate is formed from a second deposited polysilicon layer. This CMOS EPROM process employs a surprisingly few photoresist steps and is compatible with a high temperature oxidation step for making a very high quality intergate polysilicon oxide in the EPROM devices.

Method for making a self-aligned CMOS EPROM wherein the EPROM floating

A process for making an integrated cirucit EPROM having an array of EPROM devices and CMOS peripheral circuits, including blanket depositions of a first and a second polysilicon layers on a silicon substrate and removing portions of those polysilicon layers. The EPROM floating gate is made from the first polysilicon layer, and the EPROM control gate as well as the P-channel and N-channel gates of the peripheral transistors are all made from the second polysilicon layer. Independently adjustable thresholds for each of the three device types are made possible by forming an N-well at the substrate region at which the P-channel device is to be built, blanket implanting all three channels prior to selectively forming the first polysilicon layer over the EPROM region, and then selectively doping the channels of the N- and P-channel devices only.

Method of making a CMOS EPROM with independently selectable thresholds

A CMOS EPROM or the like is made wherein the basic memory device or EPROM device is an N-channel IGFET (insulated gate field effect transistor) having a control gate self-aligned with an underlying floating gate. The sources and drains of the EPROM devices as well as the sources and drains of peripheral N-channel transistors, are made by implanting with arsenic and with phosphorous. When heated, the faster diffusing phosphorous outruns, and extends from the bulk of, the arsenic so that these sources and drains extend slightly under the adjacent gate. This extension of the drain in the memory device enables a faster programming capability. A similar but oppositely directed lateral extension of all these sources and drains reduces the leakage to the substrate and reduces the chances of shorts to the substrate due to slightly misaligned metal to source and drain contacts.

Method for double doping sources and drains in an EPROM

CMOS transistors are fabricated in a P substrate using N- well regions. These wells are positioned to prevent aluminum spiking in the N channel devices. After P guard rings are formed for both P and N channel devices, additional masking and implantation are performed to produce N guard rings in the P channel devices. Before the transistors are formed, an implantation of P type impurities is performed causing the P channel devices, when they are formed, to have a PMOS buried channel.

Growing community of inventors

Doylestown, PA, United States of America

David S Pan