Micron Technology Incorporated

Intel Corporation

David S Meyaard

Lifang Xu

Matthew J King

Kunal Shrotri

Suresh Ramarajan

Jivaan Kishore Jhothiraman

Gowrisankar Damarla

Sri Sai Sivakumar Vegunta

Rithu K Bhonsle

Rutuparna Narulkar

John B Matovu

Kevin R Gast

Shashank Saraf

Deepak Thimmegowda

Owen W Jungroth

Khaled Hasnat

Liu Liu

Nanda Kumar Chakravarthi

Abhinav Tripathi

Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.

3D memory device with top wordline contact located in protected region during planarization

A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

Stair step structures including insulative materials, and related devices

Semiconductor devices including a stair step structure, and related methods

The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

Wordline bridge in a 3D memory array

Methods of forming semiconductor structures having stair step structures

Growing community of inventors

Boise, ID, United States of America

David S Meyaard