International Business Machines Corporation

Globalfoundries U.S. 2 LLC

Information Business Machines Corporation

David R Greenberg

Basanth Jagannathan

Shwu-Jen Jeng

Kathryn Turner Schonenberg

Jack Oon Chu

David Louis Harame

James Stuart Dunn

Gregory Gower Freeman

Louis DeWolf Lanzerotti

Ryan Wayne Wuthrich

Robb Allen Johnson

Douglas Duane Coolbaugh

Jeng-Bang Yau

Marwan H Khater

John Joseph Pekarik

Robert H Dennard

Jean-Olivier Plouchart

Alberto Valdes-Garcia

William R Tonti

Amlan Majumdar

Leathen Shi

Rama Divakaruni

Hiroyuki Akatsu

Seshadri Subbanna

Joseph Thomas Kocis

Samuel C Ramac

Keith M Walter

David M Rockwell

Jorg Scholvin

Hariklia Deligianni

Katherine Lynn Saenger

Christopher Vincent Jahnes

Richard Paul Volant

Scott Kevin Reynolds

Robert Allen Groves

Anil Kumar Chinthakindi

Brian Allan Floyd

Ramana Murty Malladi

Bradley Alan Orner

Jennifer L Lund

Dale K Jadus

Xudong Wang

Douglass Duane Coolbaugh

Leathen She

Amian Majumdar

An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.

Transistor structure having an electrical contact structure with multiple metal interconnect levels staggering one another

A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.

Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation

Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Multi-level interconnections for an integrated circuit chip

Radio frequency integrated circuits with on-chip noise source for use in the performance of tests and/or calibrations. A radio frequency integrated circuit includes at least one noise source residing on the radio frequency integrated circuit, the noise source being controllable by a digital input, and a radio frequency circuit residing on the radio frequency integrated circuit and being coupled to the noise source, wherein at least one attribute of the radio frequency circuit is determinable by controlling the noise source via the digital input.

Radio frequency integrated circuit with on-chip noise source for self-test

A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

Electrical contact structure having multiple metal interconnect levels staggering one another

A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology

A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.

Transistor structure with minimized parasitics and method of fabricating the same

A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

Method of fabricating self-aligned bipolar transistor having tapered collector

A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

Structure and method of self-aligned bipolar transistor having tapered collector

A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

Field effect transistor having an asymmetrically stressed channel region

Growing community of inventors

White Plains, NY, United States of America

David R Greenberg