Varian Associates, Inc.

David R Decker

Ronald L Moon

Masahiro Omori

An improved field-effect transistor is provided by forming the conducting channel boundary opposite the gate electrode as a heterojunction. For example a GaAs conducting channel may be bounded by an AlGaAs layer. The conduction electrons can penetrate the boundary very little and are constrained to the channel layer having good transport properties. The output conductance is reduced and the transconductance increased.

Heterojunction confinement field effect transistor

By positioning the source and gate electrodes on the opposite faces of the active layer, these electrodes can be brought closer together and may have their adjacent edges mutually aligned or even overlapping. The series source resistance and channel resistance can be greatly reduced, because of this closer spacing, which can not be attained when the electrodes are coplanar. By also locating the drain electrode on the same side of the active layer as the source, the source-to-drain spacing can be significantly reduced, reducing channel length and improving the high frequency performance of the transistor. Further, because the electrodes are located on both sides of the active layer, it is possible to provide a large area contact on the bottom, or substrate, side of the epitaxial wafer structure which can advantageously be used to provide a low thermal and electrical resistance connection for the source contact, for example. Finally, the fact that one or more of the electrodes can be contacted from the bottom of the wafer makes possible the simple parallel interconnection of electrodes to easily form multiple element power transistors.

Field effect transistor having source and gate electrodes on opposite

A microwave field effect transistor (FET) comprises source, gate, and drain electrodes deposited on an epitaxial layer grown on a semi-insulating substrate. The FET has lowered thermal resistance, lowered source lead inductance, and lowered gate series resistance, together with concomitant performance improvements, through the use of a novel source electrode connection which comprises a deposited or plated through metallic contact extending from the bottom of the wafer, through a hole in the substrate and epitaxial layer, to the underside of the source or other electrode which is deposited on the top side of the epitaxial layer. The chip, comprising the substrate, epitaxial layer, and top electrodes, is mounted on a heat sink. The chip's underside, including the bottom surface of the plated through source contact, is conductively bonded to the top surface of the heat sink.

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Charlottesville, VA, United States of America

David R Decker