Texas Instruments Corporation

David Permana

Jiong-Ping Lu

Changming Jin

Thomas Dyer Bonifield

Qi-Zhong Hong

Ting Yiu Tsui

Tz-Cheng Chiu

Rajesh Tiwari

Jeff A West

Scott Alexander Johannesmeyer

Albert Cheng

Brock W Fairchild

Chris M Bowles

Disclosed is a system for fabricating a semiconductor device (). An interconnect structure () is formed on the semiconductor device () and a cap () is deposited over the interconnect structure (). The interconnect structure () is annealed with the overlying cap () in place. The cap () is then removed after the interconnect structure () is annealed.

System for improving thermal stability of copper damascene structure

A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

Method of preventing seam defects in isolated lines

A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer ( ) is formed over the dielectric layer ( ). A sacrificial layer ( ) is formed over the SiC layer ( ). A trench ( ) is etched in the sacrificial layer ( ), the SiC layer ( ) and the dielectric layer ( ). A sputter etch of the sacrificial layer ( ) is used to create a wider opening at a top of the sacrificial layer ( ) than at a top of the dielectric layer ( ). A barrier layer ( ) and copper seed layer ( ) are formed. The trench ( ) is then filled with copper ( ). CMP is used to remove the excess copper ( ) and barrier layer ( ) stopping on the SiC ( ).

Use of a sacrificial layer to facilitate metallization for small features

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Dallas, TX, United States of America

David Permana