At&t Bell Laboratories

At+t Corp.

David P Favreau

Daniel J Vitkavage

Kurt George Steiner

Min-Liang Chen

John D Cuthbert

Cheryl Anne Bollinger

Jane A Swiderski

An integrated circuit has a plurality of programmable antifuses. Each antifuse can be programmed to connect metals runners on one level with either or both of a pair of runners on a second level.

Self-aligned vertical antifuse

A layer of spin-on-glass is used as a hard mask for patterning an underlying layer of polysilicon. The patterned polysilicon may be used in the gate structures of field effect transistors.

Integrated circuit process using a 'hard mask'

Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.

Integrated circuit with planar dielectric layer

An integrated circuit design and method for its fabrication are disclosed. A bilevel-dielectric is formed to cover the active regions of a transistor and raised topographic features such as a gate runner. The upper level of the dielectric is planarized to provide for easier subsequent multilevel-conductor processing. Windows are opened in the bilayer dielectric by etching through the upper level of the dielectric, stopping on the lower level of the dielectric. Then the etch procedure is continued to etch through the lower level of the dielectric.

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Coopersburg, PA, United States of America

David P Favreau