Applied Materials, Inc.

Bell Telephone Laboratories

David N Wang

Dan Maydan

John M White

Mei Yin Chang

Kam S Law

Cissy S Leung

Kenneth S Collins

Ilya Perlov

Salvador P Umotoy

John A Adamik

Sasson Roger Somekh

David K Cheng

Jerry Yuen Wong

Jeffrey S Marks

Peter W Lee

Masato M Toshima

Makoto Nagashima

Kazuto Fukuma

Isaac Harari

Peter D Hoppe

Lawrence C Lei

Craig A Roderick

Hyman J Levinstein

Chan-Lon Yang

Vladimir J Zeitlin

Dana L Andrews

Kenneth R Stalder

Tetsuya Sato

Frank D Egitto

Alfred W Mak

Daniel L Flamm

Ashok K Sinha

Joseph M Moran

Arthur C Adams

Simon W Tam

Jerry Yuen-Kui Wong

Tatsuya Sato

Mei Cheng

Cesar D Capio

Dan Mayden

Nadia Lifshitz

Robert Foster

Ching C Tang

Toung K Leong, Deceased

T K Leong, Deceased

Peter P Leong, Executor

Ronald P Reade

An inlet gas manifold for a vacuum deposition chamber incorporates inlet apertures which increase in diameter or cross-section transverse to the direction of gas flow. The aperture configuration increases the dissociation gases such as nitrogen and, thus increases the rate of silicon nitride deposition provided by nitrogen gas chemistry, without requiring the use of reactants such as ammonia. While one could use ammonia in the deposition gas chemistry if desired, the process provides the option of completely eliminating ammonia. The inlet manifold containing the increasing-diameter gas inlet holes provides enhanced control of the process and the deposited film, and is also useful for forming other dielectrics such as silicon oxide and silicon oxynitride. In particular, silicon oxynitride films are characterized by low hydrogen content and by compositional uniformity.

PECVD of compounds of silicon from silane and nitrogen

An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R--.THETA. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.

Multiple chamber integrated process system

A process for etching single crystal silicon, polysilicon, silicide and polycide using iodinate or brominate gas chemistry, is disclosed. The iodinate/brominate gas chemistry etches narrow deep trenches with very high aspect ratios and good profile control and without black silicon formation or other undesirable phenomena.

Bromine and iodine etch process for silicon and silicides

A method for protecting a selected area of a substrate against deposition on the selected area. The method includes the steps of flowing a process gas into a substrate processing chamber and flowing a purge gas to the selected area of the substrate to prevent the process gas from contacting the selected area or minimize contact between the process gas and the selected area. In various embodiments the selected area is a backside periphery of the substrate or the edge of the substrate. Also in these embodiments, the process gas is flowed into a deposition zone in order to deposit a thin film layer over an upper surface of the substrate, and a flow of the process and purge gas is established such that the process gas flows radically across the upper surface of the substrate, combines with the purge gas near an edge of the substrate and exits the processing chamber through an exhaust system.

Method for protecting against deposition on a selected region of a

An inlet gas manifold for a vacuum deposition chamber incorporates inlet apertures which increase in diameter or cross-section transverse to the direction of gas flow. The aperture configuration increases the dissociation gases such as nitrogen and, thus increases the rate of silicon nitride deposition provided by nitrogen gas chemistry, without requiring the use of reactants such as ammonia. While one could use ammonia in the deposition gas chemistry if desired, the process provides the option of completely eliminating ammonia. The inlet manifold containing the increasing-diameter gas inlet holes provides enhanced control of the process and the deposited film.

PECVD of silicon nitride films

A substrate processing reactor capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and other substrate processing operations all of which can either be performed separately or as part of in-situ multiple step processing. The reactor incorporates a uniform radial gas pumping system which enables uniform reactant gas flow across the wafer. Also included are upper and lower purge gas dispersers. The upper purge gas disperser directs purge gas flow downwardly toward the periphery of the wafer while the lower gas disperser directs purge gas across the backside of the wafer. The radial pumping gas system and purge gas dispersers sweep radially away from the wafer to prevent deposition external to the wafer and keep the chamber clean.

Apparatus for preventing deposition gases from contacting a selected

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

Plasma-enhanced CVD process using TEOS for depositing silicon oxide

A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dopants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.

Boron phosphorus silicate glass composite layer on semiconductor wafer

A high pressure, high throughout, single wafer semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature process for forming a highly conformal layer of silicon dioxide from a plasma of TEOS, oxygen and ozone is also disclosed. This layer can be planarized using an etchback process. Silicon oxide deposition and etchback can be carried out sequentially in the reactor.

Thermal chemical vapor deposition of silicon dioxide and in-situ

A two step process is disclosed for forming a silicon oxide layer over a stepped surface of a semiconductor wafer while inhibiting the formation of voids in the oxide layer which comprises depositing a layer of an oxide of silicon over a stepped surface of a semiconductor wafer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3, and tetraethylorthosilicate as the gaseous source of silicon while maintaining the pressure in the CVD chamber within a range of from about 250 Torr to about 760 Torr and then depositing a second layer of oxide over the first layer in a CVD chamber by flowing into the chamber a gaseous mixture comprising a source of oxygen, a portion of which comprises O.sub.3 ; and tetraethylorthosilicate as the gaseous source of silicon while maintaining the CVD chamber at a lower pressure than during the first deposition step.

Two step process for forming void-free oxide layer over stepped surface

An improved method of fabricating integrated circuit structures on semiconductor wafers using a plasma-assisted process is disclosed wherein the plasma is generated by a VHF/UHF power source at a frequency ranging from about 50 to about 800 MHz. Low pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out within a pressure range not exceeding about 500 milliTorr; with a ratio of anode to cathode area of from about 2:1 to about 20:1, and an electrode spacing of from about 5 cm. to about 30 cm. High pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out with a pressure ranging from over 500 milliTorr up to 50 Torr or higher; with an anode to cathode electrode spacing of less than about 5 cm. By carrying out plasma-assisted processes using plasma operated within a range of from about 50 to about 800 MHz, the electrode sheath voltages are maintained sufficiently low, so as to avoid damage to structures on the wafer, yet sufficiently high to preferably permit initiation of the processes without the need for supplemental power sources. Operating in this frequency range may also result in reduction or elimination of microloading effects.

UHF/VHF plasma for use in forming integrated circuit structures on

An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R-.theta. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.

Multichamber integrated process system

A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer if insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Method for planarizing an integrated circuit structure using low melting

Gas chemistry and a related RIE mode process is described for etching silicides of the refractory metals titanium, tantalum, tungsten and aluminum and for etching composites of these silicides on polycrystalline silicon layers. BCl.sub.3 is added to the HCl/Cl.sub.2 gas chemistry used for the polysilicon etch along with additives selected from fluorinated gases and oxygen to satisfy the multiple requirement of the two-step silicide-polysilicon etch process, including the silicide-to-polysilicon etch ratio requirement.

Materials and methods for etching silicides, polycrystalline silicon and

A magnetic field enhanced single wafer plasma etch reactor is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring. The lift pins and clamp ring are moved vertically by a one-axis lift mechanism to accept the wafer from a cooperating external robot blade, clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode and a thermal conductivity-enhancing gas parallel-bowed interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode. A gas feed-through device applies the cooling gas to the RF powered electrode without breakdown of the gas. Protective coatings/layers of materials such as quartz are provided for surfaces such as the clamp ring and gas manifold. The combination of these features provides a wide pressure regime, high etch rate, high throughput single wafer etcher which provides uniformity, directionality and selectivity at high gas pressures, operates cleanly and incorporates in-situ self-cleaning capability.

Magnetic field-enhanced plasma etch reactor

Growing community of inventors

Cupertino, CA, United States of America

David N Wang