General Electric Company

Other

David N Ludington

Samuel C Wang

The invention relates to a multiple channel readout circuit optimized for a cryogenically operated IR sensor head. The circuit is applicable to the individual channel preamplifiers of a charge injection device (CID) IR sensor. Since the thermal leakage must be minimized, the voltages on the principal current supply path to the individual preamplifiers will vary when a strong signal is present on any channel. Crosstalk is avoided by using a four transistor cascode preamplifier circuit having a source follower output, in which the gate of the transistor, which acts as a load to the two cascoded transistors, is isolated from the drain of the load transistor, connected to a gate load node common to the other channels, and the node connected via a single connection of high thermal impedance to a terminal external to the cryogenic environment, at which filtering may be provided as needed.

Multiple channel readout circuit optimized for a cryogenically operated

The invention relates to a charge injection device for optical sensing including a novel readout circuit facilitating an extended dynamic range. The invention has primary application to linear arrays for IR sensing. Sensitive, low-level operation is achieved in a primary readout means by allowing the charge to accumulate in the potential well of the individual sensor elements over the line period with each element being reset at the pixel readout rate and by using a charge injection pulse to clear stored charge from the individual sensor elements. A secondary readout means is also provided in which the charge is allowed to accumulate over a period not exceeding the pixel readout interval for unsaturated large signal operation and by sensing the change in depth of the potential well. The two readout means are combined in the eventual display to provide an improvement of typically three orders of magnitude in the dynamic range of the CID.

Readout circuit for an optical sensing charge injection device

A one bit memory for bipolar signals is disclosed comprising one channel which samples the positive portion of an input signal and another channel which samples the negative portion of the input signal. Having stored a one bit sample in a separate shift register for each channel, the three level output signal is obtained by combining the outputs of each shift register.

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New Hartford, NY, United States of America

David N Ludington