Ltx Corporation

David Menis

Phillip D Burlison

Mark E Deome

Tommie Edward Berry

Christopher Joel Hannaford

David W Curry

Eric H Rosenfeld

H Neil Kelly

Jeffrey H Perkins

Edward J Terrenzi

Kenneth J Lanier

Roger W Blethen

Michael Carlyle Davis

Donald Vick Organ

Michael Gordon Davis

William R DeHaven

Harold S Vitale

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

An apparatus for a test system for testing an electronic circuit. The apparatus includes an interconnect path, a comparator, a programmable apparatus, a first Schottky diode, and a second Schottky diode. The interconnect path has a first end and a second end. The first end of the interconnect path is coupled to the electronic circuit under test. The interconnect path transmits a signal from the electronic circuit under test to the second end of the interconnect path. The comparator is coupled to the second end of the interconnect path for receiving and comparing the signal from the electronic circuit under test with a reference voltage. The comparator has a high input impedance. The comparator provides an output signal to the test system. The programmable apparatus provides a selectable first voltage and a selectable second voltage. A first Schottky diode is provided for reducing ringing of the signal from the electronic circuit under test. A first end of the first Schottky diode is coupled to the interconnect path at a point near the comparator. A second end of the first Schottky diode is coupled to the selectable first voltage. A second Schottky diode is provided for reducing ringing of the signal from the electronic circuit under test. A first end of the second Schottky diode is coupled to the selectable second voltage. The second end of the second Schottky diode is coupled to the interconnect path at a point near the comparator.

Test system apparatus with Schottky diodes with programmable voltages

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Cohasset, MA, United States of America

David Menis