Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Amkor Technologies, Inc.

David McCann

Robert Francis Darveaux

Louis W Nicholls

John McCormick

Paul Robert Hoffman

Richard L Groover

An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.

Fine pitch copper pillar package and method

A thermally enhanced, chip-scale, Lead-on-Chip ('LOC') semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another for even greater thermal and electrical conductivity.

Thermally enhanced chip scale lead on chip semiconductor package and method of making same

A thermally enhanced, chip-scale, Lead-on Chip ('LOC') semiconductor packages includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another for even greater thermal and electrical conductivity.

A micromachine package includes a micromachine chip having a front surface and a micromachine area on the front surface. The micromachine package further includes a substrate having at least one vent extending through the substrate. A seal layer extends between the front surface of the micromachine chip and an upper surface of the substrate. The vent extends to the seal layer directly opposite of a cavity defined by an upper surface of the seal layer and the front surface of the micromachine chip. The micromachine area is located within the cavity.

Flip-chip micromachine package using seal layer

A thermally enhanced, chip-scale, Lead-on-Chip (&ldquo;LOC&rdquo;) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semi-conductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another.

Growing community of inventors

Chandler, AZ, United States of America

David McCann