International Business Machines Corporation

Siemens Aktiengesellschaft

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Kabushiki Kaisha Toshiba

Infineon Technologies Ag

David M Dobuzinsky

Herbert Lei Ho

Son Van Nguyen

Munir D Naeem

Jeffrey P Gambino

Jack Allan Mandelman

Richard Stephan Wise

Johnathan E Faltermeier

Byeong Yeol Kim

David L Harmon

Erwin Hammerl

Kangguo Cheng

Tue H Nguyen

Richard Anthony Conti

Michael D Armacost

Chienfan Yu

James F Moseman

Tetsuo Matsuda

Jay William Strane

Mark A Jaso

Philip L Flaitz

Michael D Steigerwalt

Herbert Palm

Yoichi Otani

Michael Maldei

Samuel C Ramac

Prakash Chimanlal Dev

Stephen G Fugardi

John Preston Benedict

Denise Pendleton

Effendi Leobandung

Daniel C Edelstein

Laertis Economikos

Pai-Hung Pan

Gary Bela Bronner

Chandrasekhar Narayan

Donald M Kenney

Hiroyuki Akatsu

Scott David Halle

Katsuya Okumura

Tokuhisa Ohiwa

Stephan Alan Cohen

Tsukasa Azuma

Siddhartha Panda

Alexander William Simpson

Mahender Kumar

Atul Champaklal Ajmera

William C Wille

Gill Yong Lee

Hiroshi Takato

Peter D Hoh

Radhika Srinivasan

Brian L Tessier

Kenneth C Arndt

Karen P Madden

Peter Wrschka

Kia-Seng Low

Padraic C Shafer

Seiko Yoshida

Srinandan R Kasi

Carl John Radens

David V Horak

Steven J Holmes

Yun Yu Wang

Mark Charles Hakey

Ravikumar Ramachandran

Rolf Weis

Babar Ali Khan

Jochen C Beintner

Michael Jay Shapiro

Viraj Yashawant Sardesai

Rama Divakaruni

James Gardner Ryan

Larry Alan Nesbit

Alvin Wayne Strong

Thomas Safron Kanarsky

Arpan Pravin Mahorowala

Gregory Costrini

Xi Li

Rajesh Rengarajan

Christopher D Sheraw

Jeremy K Stephens

Joyce C Liu

Roy Charles Iggulden

Willard E Conley

Donna Rizzone Cote

Tina Jane Wagner

Hung Y Ng

John Chester Malinowski

Larry Clevenger

Ronald Anthony DellaGuardia

Michael L Passow

Dung-Ching Perng

Munir-ud-Din Naeem

Paul Wensley

Karen Ann Bard

Thomas Rupp

Jeffery Peter Gambino

Michael M Iwatake

Keith K H Wong

A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.

Embedded DRAM memory cell with additional patterning layer for improved strap formation

The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.

A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

Vertical SOI trench SONOS cell

A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

Shallow trench isolation structure compatible with SOI embedded DRAM

A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

Poly filled substrate contact on SOI structure

Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

Methods for enhancing trench capacitance and trench capacitor

Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

STI formation in semiconductor device including SOI and bulk silicon regions

A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects.

Formation of controlled sublithographic structures

A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.

SOI trench capacitor cell incorporating a low-leakage floating body array transistor

An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device

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Hopewell Junction, NY, United States of America

David M Dobuzinsky