International Business Machines Corporation

Infineon Technologies Ag

Advanced Micro Devices Corporation

Adeia Semiconductor Bonding Technologies Inc.

David Lee Rath

Elbert Emin Huang

Rangarajan Jagannathan

Kenneth John McCullough

Harald F Okorn-Schmidt

Benjamin David Briggs

John Anthony Fitzsimmons

Cornelius Brown Peethala

Daniel C Edelstein

Keith Randal Pope

Karen P Madden

Chih-Chao Yang

Shom Ponoth

Sampath Purushothaman

Satyanarayana Venkata Nitta

Emanuel Israel Cooper

Raghuveer Reddy Patlolla

Andrew Herbert Simon

Ravikumar Ramachandran

Bruce Kenneth Furman

Sivananda K Kanakasabapathy

Ruqiang Bao

Andrew Mark Greene

Rajasekhar Venigalla

Shyng-Tsong Chen

Stephan Grunow

Nicholas C Fuller

Kisup Chung

Glenn Walton Gale

Devendra K Sadana

Takeshi Nogami

Hosadurga K Shobha

Griselda Bonilla

Muthumanickam Sankarapandian

Anna Wanda Topol

Mahadevaiyer Krishnan

Cornelia K Tsang

Kaushik Arun Kumar

Kuan-Neng Chen

Vivekananda P Adiga

Qiang Huang

Satyavolu S Papa Rao

Wei-Tsu Tseng

Russell Herbert Arndt

Kenneth M Davis

Kathryn C Fisher

Ali Afzali-Ardakani

Timothy Joseph Dalton

Katherine Lynn Saenger

Eugene John O'Sullivan

Cheng-Wei Cheng

Sandra Guy Malhotra

Kuen-Ting Shiu

Naigang Wang

Chandrasekhar Narayan

Brent A Wacaser

Michael F Lofaro

Martin O Sandberg

Raymond R Horton

Michael J Palmer

Chao-Kun Hu

Hongwen Yan

Ismail C Noyan

Kurt R Grebe

George Gabriel Totir

Judith Marie Rubino

Linda C Matthew

Fen Fen Jamin

Scott Alan Estes

David V Horak

Theodorus E Standaert

Keith Kwong Hon Wong

Oscar Van Der Straten

Kenneth Parker Rodbell

Jeng-Bang Yau

Matthew Earl Colburn

Sanjay C Mehta

Su Chen Fan

Ronald G Filippi

Terry Allen Spooner

Donald Francis Canaperi

Sarunya Bangsaruntip

Richard Anthony Conti

Willi Volksen

Robert L Bruce

Stephen Edward Greco

Michael C Gaidis

Teddie Peregrino Magbitang

Charles Thomas Black

Kaushik Chanda

Charles Jesse Taft

Kamalesh K Srivastava

Gregory Costrini

John C Collins

Geraud Jean-Michel Dubois

Henry Atkinson Nye, Iii

Daewon Yang

John Bruley

Sujatha Sankaran

Michael Beck

Devices, systems, methods, and/or computer-implemented methods that can facilitate protection of a substrate in a qubit device using sacrificial material are provided. According to an embodiment, a device can comprise a superconducting lead provided on a pillar of a sacrificial material provided on a substrate. The device can further comprise a collapsed superconducting junction provided on the substrate and coupled to the superconducting lead.

Sacrificial material facilitating protection of a substrate in a qubit device

Techniques regarding methods and/or apparatuses for protecting metal substrates during one or more lithography processes are provided. For example, one or more embodiments described herein can comprise a method that can include coating a metal substrate with a polymer film that self-assembles on a metal oxide positioned on a surface of the metal substrate. The method can also include covalently bonding the polymer film to the metal oxide.

Metal surface protection

A method for fabricating a bridge structure in a quantum mechanical device includes providing a substructure including a substrate having deposited thereon a layer of a first superconducting material divided into a first portion, a second portion and a third portion that are electrically insulated from each other; depositing a sacrificial layer on the substructure; electrically connecting the first portion and the second portion with a strip of a second superconducting material, the second superconducting material being different from the first superconducting material; and removing a portion of the sacrificial layer so as to form a bridge structure over the third portion between the first portion and the second portion, the bridge structure electrically connecting the first portion to the second portion while not electrically connecting the third portion to the first portion and not electrically connecting the third portion to the second portion.

Microfabricated air bridges for quantum circuits

A three dimensional (3D) In-Silicon energy storage device is provided by a method that includes forming a thick dielectric material layer on a surface of a silicon based substrate. A 3D trench is then formed into the dielectric material layer and the silicon based substrate, and thereafter a dielectric material spacer is formed, in addition to the dielectric remaining on the field of the substrate, as well as along a sidewall of the 3D trench, and on a first portion of a sub-surface of the silicon based substrate that is present at a bottom of the 3D trench. A second portion of the sub-surface of the silicon based substrate that is present in the 3D trench remains physically exposed. Active energy storage device materials can then be formed laterally adjacent to the dielectric material spacer that is within the 3D trench and on the dielectric material layer.

High throughput insulation of 3D in-silicon high volumetric energy and power dense energy storage devices

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

Additive core subtractive liner for metal cut etch processes

An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

A method of making a Josephson junction in a superconducting qubit includes providing a substrate having a convex structure with a first face and a second face meeting at an edge; depositing a first layer of superconducting material on the first face; oxidizing the first layer to form a layer of oxide material on a surface of the first layer; and depositing a second layer of the superconducting material on the second face. A portion of the second layer is in contact with a portion of the layer of oxide material at or in the vicinity of the edge such that the portion of the layer of oxide material is sandwiched between a portion of the first layer and the portion of the second layer to define a Josephson junction at or in the vicinity of the edge.

Transmon qubits with self defined junctions

Enhanced compositions and methods are provided for selectively etching silicon wafers, which is particularly useful in the context of silicon wafer manufacturing and processing applications. Optionally, a formulation is provided which selectively etches silicon dioxide in preference to aluminum oxide. Optionally, a formulation and method are provided that is substantially non-aqueous.

Selective etch formulation for silicon oxide

A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.

Low aspect ratio interconnect

A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.

Interconnect structures with fully aligned vias

A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and forming an interface layer over the barrier layer. A main conductor is formed over the interface layer, and the main conductor is recessed selectively to the interface layer and the barrier layer to a position below a top surface of the dielectric layer. The interface layer is selectively wet etched to the main conductor and the barrier layer using a chemical composition having an oxidizer, wherein the chemical composition is buffered to include a pH above 7. The barrier layer is selectively etching to the main conductor and the interface layer.

Wet etch removal of Ru selective to other metals

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Stormville, NY, United States of America

David Lee Rath